;PALASM Design Description

;---------------------------------- Declaration Segment ------------
TITLE    186ES PCnet-ISA Glue Logic
PATTERN  
AUTHOR   Mark Bowers, FAE Atlanta
COMPANY  Advanced Micro Devices, inc.
DATE     3/19/96

REVISION HISTRY
; 3/19/96       MB - CREATED
; 3/28/96       MB - add 85C30 support, use 186ES
; 4/8/96        MB - included digital one-shot for sbhe_
; 5/7/96        MB - fixed mistake w/ I/O slave reads (added PCS3,
;                    removed rd_)
; 5/7/96        MB - added support for PCnet byte writes (added ADX0)
; 5/7/96        MB - fixed mistake on sbhe tristate
; 7/25/96       MB - took out 85C30, converted from 16V8 to 22V10
; 11/7/96       MB - went back to I/O mapped
; 11/18/96      MB - changed to support 16 bit SRAM, swapped pins to match
;                    schematic
; 11/27/96      MB - swapped pins (again) to match schematic
; 1/24/97       MB - swapped pins (yet again) to match schematic

CHIP  es_pcnet  PALCE22V10

;Note DIP pinout for SSOP 

;---------------------------------- PIN Declarations ---------------
;    DIP                 PLCC
PIN  1          clka    ;2 - clk from 186ES     
PIN  2          master_ ;3 - from PCnet, indicates PCnet has bus
PIN  3          lcs_    ;4 - lower chip select from 186ES, addresses memory
PIN  4          hlda    ;5 - from 186ES, inverted to DACK* on PCnet
PIN  5          bhe_    ;6 - Byte High Enable from 186ES
PIN  6          wlb_    ;7 - Write Low Byte from 186ES
PIN  7          whb_    ;9 - Write High Byte from 186ES
PIN  8          mcs0_   ;10 - /MCS0, not used in this design, could be used
;                             to memory map PCnet-ISA
PIN  9          pcs2_   ;11 - peripheral CS from 186ES
PIN  10         pcs3_   ;12 - peripheral CS from 186ES

PIN  16         dbhe_   ;19 - Delayed bhe_, external N/C
PIN  17         aen_    ;20 - Address Enable to PCnet
PIN  20         sbhe_   ;24 - System Byte High Enable on PCnet and SRAM
PIN  21         hlda_   ;25 - connected to DACK* on PCnet
PIN  22         memw_   ;26 - Memory Write drives SRAM when ES has bus         
PIN  23         rcs_    ;27 - ram chip select




;----------------------------------- Boolean Equation Segment ------
EQUATIONS

hlda_ = /hlda

/rcs_ = /lcs_ + /master_        ;lcs_ doesn't tristate on a bus hold

;PCS2 and PCS3 assert when the 186ES address is x2xxh and x3xx respectively.
;This is the I/O space that we want to talk to the PCnet-ISA in.
/aen_ = /pcs2_ + /pcs3_         

;The signal memw_ drives the R/W line on the SRAM.  When the 186ES has the
;bus, this is simply a logical AND of whb_ and wlb_.  The 186ES signal /WR
;can NOT be used because the pulse width is too short at 40MHz.
/memw_ = /whb_ + /wlb_
memw_.TRST = master_

;To support 8 bit I/O cycles to the PCnet-ISA, SBHE must be asserted before
;IOR or IOW. To conform to the ISA spec, SBHE is extended so the trailing
;edge occurs after IOR or IOW goes high.  The signal sbhe is tristated when
;PCnet has the bus.
dbhe_ := bhe_
/sbhe_ = /bhe_ + /dbhe_
sbhe_.TRST = master_