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GeodeLink System Architecture
AMD announces its top-to-bottom system architecture for systemon- a chip.
The AMD GeodeLink™ architecture offers a single on-chip interconnect
that facilitates the integration of modules and allows the use of Unified
Memory Architecture (UMA).
Unified Memory Architecture (UMA)
At the heart of the GeodeLink architecture is the built-in arbiter. The
arbiter enables dynamic allocation of memory bandwidth, with “on-the-fly”
prioritization. Use of out-of-order data streams coupled with a high-performance
peer-to-peer communication enables direct communication between modules,
resulting in more efficient use of shared memory.
On-Chip Switched Fabric
At the core of the GeodeLink architecture lies a very highbandwidth interface
unit that can handle up to 6 GB/s of data transfer. With up to 31 pipelined
transactions, the architecture increases the level of performance by allowing
devices to have multiple simultaneous outstanding requests. This single
bus architecture improves performance and facilitates IP reusability,
thus improving our customers’ time-to-market.
Advanced Hardware Power Management (AHPM)
The GeodeLink architecture has embedded power management features. This
allows our OEM and ODM customers to take advantage of advanced power management
without writing a single line of code. It is also OS independent, since
the power management calls are handled at the BIOS level.
Development Software
The GeodeLink architecture has an embedded Enhanced JTAG interface that
provides a consistent debug environment. With full bus master access and
branch trace messaging capabilities, software development can be significantly
accelerated.
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