8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory

General Description
The Am29LV800D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt V_CC supply to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.

Distinctive Characteristics

• Single power supply operation
  • 2.7 to 3.6 volt read and write operations for battery-powered applications
• Manufactured on 0.23 µm process technology
  • Compatible with 0.32 µm Am29LV800 device
• High performance
  • Access times as fast as 70 ns
• Ultra low power consumption (typical values at 5 MHz
  • 200 nA Automatic Sleep mode current
  • 200 nA standby mode current
  • 7 mA read current
  • 15 mA program/erase current
• Flexible sector architecture
  • One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode)
  • One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode)
  • Supports full chip erase
  • Sector Protection features:
    • A hardware method of locking a sector to prevent any program or erase operations within that sector
    • Sectors can be locked in-system or via programming equipment
    • Temporary Sector Unprotect feature allows code changes in previously locked sectors
• Unlock Bypass Program Command
  • Reduces overall programming time when issuing multiple program command sequences
• Top or bottom boot block configurations available
• Embedded Algorithms
  • Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
  • Embedded Program algorithm automatically writes and verifies data at specified addresses
• Minimum 1 million write cycle guarantee per sector
• 20-year data retention at 125° C
  • Reliable operation for the life of the system
• Package option
  • 48-ball FBGA
  • 48-pin TSOP
  • 44-pin SO
• Compatibility with JEDEC standards
  • Pinout and software compatible with single-power supply Flash
  • Superior inadvertent write protection
• Data# Polling and toggle bits
  • Provides a software method of detecting program or erase operation completion
• Ready/Busy# pin (RY/BY#)
  • Provides a hardware method of detecting program or erase cycle completion
• Erase Suspend/Erase Resume
  • Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Hardware reset pin (RESET#)
  • Hardware method to reset the device to reading array data