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Am42BDS6408G Product Overview
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29BDS640G 64 Megabit (4 M x 16Bit) CMOS 1.8 Voltonly, Simultaneous Operation,
Burst Mode Flash Memory and 8 Mbit (512 K x 16-Bit) Static RAM
General Description
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. A 12.0-volt VID may be used for faster program performance if desired. The device can also be programmed in standard EPROM programmers.
Distinctive Characteristics
| MCP Features |
Architectural Advantages |
Package Options |
Performance Characteristics |
Software Features |
Hardware Features |
SRAM Features |
|
MCP Features
- Power supply voltage of 1.65 to 1.95 volt
- High performance
- Access time as fast as 70 ns
- Package
- Operating Temperature
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Flash Memory Features
Architectural Advantages
- Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
- Manufactured on 0.17 µm process technology
- Simultaneous Read/Write operations
- Data can be continuously read from one bank while executing erase/program functions in other bank
- Zero latency between read and write operations
- Four bank architecture: 16Mb/16Mb/16Mb/16Mb
- Programmable Burst Interface
- 2 Modes of Burst Read Operation
- Linear Burst: 8, 16, and 32 words with wrap-around
- Continuous Sequential Burst
- Sector Architecture
- Eight 8 Kword sectors and one hundred twenty-six 32 Kword sectors
- Banks A and D each contain four 8 Kword sectors and thirty-one 32 Kword sectors; Banks B and C each contain thirty-two 32 Kword sectors
- Eight 8 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range
- Minimum 1 million erase cycle guarantee per sector
- 20-year data retention at 125°C
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Package Options
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Performance Characteristics
- Read access times at 54/40 MHz
- Burst access times of 13.5/20 ns @ 30 pF at industrial temperature range
- Asynchronous random access times of 70 ns (at 30 pF)
- Synchronous latency of 87.5/95 ns
- Power dissipation (typical values, CL = 30 pF)
- Burst Mode Read: 10 mA
- Simultaneous Operation: 25 mA
- Program/Erase: 15 mA
- Standby mode: 0.2 µA
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Software Features
- Supports Common Flash Memory Interface (CFI)
- Software command set compatible with JEDEC 42.4 standards
- Data# Polling and toggle bits
- Erase Suspend/Resume
- Suspends or resumes an erase operation in one sector to read data from, or program data to, other sectors
- Unlock Bypass Program command
- Reduces overall programming time when issuing multiple program command sequences
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Hardware Features
- Software command sector locking
- Handshaking: host monitors operations via RDY output
- Hardware reset pin (RESET#)
- WP# input
- Write protect (WP#) function protects sectors 0, 1 (bottom boot) or sectors 132 and 133 (top boot), regardless of sector protect status
- ACC input: Acceleration function reduces programming time; all sectors locked when ACC = VIL
- CMOS compatible inputs, CMOS compatible outputs
- Low VCC write inhibit
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SRAM Features
- Power dissipation
- Operating: 2 mA typical
- Standby: 0.2 µA typical
- CE1s# and CE2s Chip Select
- Power down features using CE1s# and CE2s
- Data retention supply voltage: 1.0 to 2.2 volt
- Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
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