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S29PL127J/S29PL129J/S29PL064J/S29PL032J Product Overview
128/128/64/32 Megabit (8/8/4/2
M x 16 Bit) CMOS 3.0 Volt only, Simultaneous Read/Write Flash Memory with
Enhanced VersatileIO™ Control
General Description
The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page
Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2
Mwords. The devices are offered in the following packages:
- 11mm x 8mm, 64-ball Fine-pitch BGA standalone (all)
- 9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J and PL129J)
- 8mm x 11.6mm, 64-ball Fine pitch BGA multi-chip compatible (PL127J/PL129J)
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed
in-system or in standard EPROM programmers. A 12.0 V VPP is not required
for write or erase operations.
Distinctive Characteristics
Architectural Advantages
- 128/128/64/32 Mbit Page Mode devices
- Page size of 8 words: Fast page read access from random locations
within the page
- Single power supply operation
- Full Voltage range: 2.7 to 3.6 volt read, erase, and program operations
for battery-powered applications
- Dual Chip Enable inputs (only in PL129J)
- Two CE# inputs control selection of each half of the memory space
- Simultaneous Read/Write Operation
- Data can be continuously read from one bank while executing erase/program
functions in another bank
- Zero latency switching from write to read operations
- FlexBank Architecture (PL127J/PL064J/PL032J)
- 4 separate banks, with up to two simultaneous operations per device
- Bank A:
- PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
- PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
- PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
- Bank B:
- PL127J - 48 Mbit (32 Kw x 96)
- PL064J - 24 Mbit (32 Kw x 48)
- PL032J - 12 Mbit (32 Kw x 24)
- Bank C:
- PL127J - 48 Mbit (32 Kw x 96)
- PL064J - 24 Mbit (32 Kw x 48)
- PL032J - 12 Mbit (32 Kw x 24)
- Bank D:
- PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31)
- PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15)
- PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7)
- FlexBank Architecture (PL129J)
- 4 separate banks, with up to two simultaneous operations per device
- CE#1 controlled banks:
- Bank 1A:
- PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
- Bank 1B:
- PL129J - 48Mbit (32Kw x 96)
- CE#2 controlled banks:
- Bank 2A:
- PL129J - 48 Mbit (32Kw x 96)
- Bank 2B:
- PL129J - 16Mbit (4Kw x 8 and 32Kw x 31)
- Enhanced VersatileI/OTM (VIO) Control
- Output voltage generated and input voltages tolerated on all control
inputs and I/Os is determined by the voltage on the VIO
pin
- VIO options at 1.8 V and 3 V I/O for PL127J and PL129J
devices
- 3V VIO for PL064J and PL032J devices
- SecSiTM (Secured Silicon) Sector region
- Up to 128 words accessible through a command sequence
- Up to 64 factory-locked words
- Up to 64 customer-lockable words
- Both top and bottom boot blocks in one device
- Manufactured on 110 nm process technology
- Data Retention: 20 years typical
- Cycling Endurance: 1 million cycles per sector typical
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Performance Characteristics
- High performance
- Page access times as fast as 20 ns
- Random access times as fast as 55 ns
- Power consumption (typical values at 10 MHz)
- 45 mA active read current
- 17 mA program/erase current
- 0.2 µA typical standby mode current
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Software Features
- Software command-set compatible with JEDEC 42.4 standard
- Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families
and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families
- CFI (Common Flash Interface) compliant
- Provides device-specific information to the system, allowing
host software to easily reconfigure for different Flash devices
- Erase Suspend / Erase Resume
- Suspends an erase operation to allow read or program operations
in other sectors of same bank
- Unlock Bypass Program command
- Reduces overall programming time when issuing multiple program
command sequences
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Hardware Features
- Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or erase cycle
completion
- Hardware reset pin (RESET#)
- Hardware method to reset the device to reading array data
- WP#/ ACC (Write Protect/Acceleration) input
- At VIL, hardware level protection for the first and
last two 4K word sectors.
- At VIH, allows removal of sector protection
- At VHH, provides accelerated programming in a factory
setting
- Persistent Sector Protection
- A command sector protection method to lock combinations of individual
sectors and sector groups to prevent program or erase operations
within that sector
- Sectors can be locked and unlocked in-system at VCC level
- Password Sector Protection
- A sophisticated sector protection method to lock combinations
of individual sectors and sector groups to prevent program or erase
operations within that sector using a user-defined 64-bit password
- Package options
- Standard discrete pinouts
- 11 x 8 mm, 80-ball Fine-pitch BGA (PL127J/PL129J (VBG080)
- 8 x 6 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048)
- MCP-compatible pinout
- 8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J and PL129J)
- 7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J)
- Compatible with MCP pinout, allowing easy integration of
RAM into existing designs
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