Architectural Advantages

• Single 1.8 volt read, program and erase (1.70 to 1.95 volt)
• Multiplexed Data and Address for reduced I/O count
  • A15–A0 multiplexed as DQ15–DQ0
  • Addresses are latched by AVD# control input when CE# lo
• Manufactured on 110 process technology
• Simultaneous Read/Write operation
  • Data can be continuously read from one bank while executing erase/program functions in another bank
  • Zero latency between read and write operations 
• Programable Burst Interface
  • Linear Burst: 32, 16, and 8 words with wrap around
  • Linear Burst: 32, 16, and 8 words without wrap around
  • Continuous Sequential Burst
• Sector Architecture
• Four 8 Kword sectors
• Two hundred fifty-five (S29NS128J), one hundred twenty-seven (S29NS064J),sixty-three (S29NS032J), or thirty-one (S29NS016J) 32 Kword sectors
• 1,000,000 cycles per sector typical
• Data Retention: 20-year typical
• Packages
• 48-ball Very Thin FBGA (S29NS128J)
• 44-ball Very Thin FBGA (S29NS064J, S29NS032J, S29NS016J

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Performance Characteristics

• Read access times at 66/54 MHz (CL=30 pF)
  • Burst access times of 11/13.5 ns at industrial temperature range
  • Asynchronous random access times of 65/70 ns
  • Synchronous random access times of 71/87.5 n
• Typical Programming
  • Single word programming time of 9 µs
  • Sector erase time of 200 ms for 8 Kword sectors and 400 ms sector erase time for 32 Kword sectors
• Power dissipation (typical values, 8 bits switching, CL = 30 pF)
  • Burst Mode Read: 25 Ma
  • Simultaneous Operation: 40 mA
  • Program/Erase: 15 mA—Standby mode: 9 µA

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Hardware Features

• Software command sector locking
• Write protect (WP#) function allows protection of two highest boot sectors,
• Handshaking feature available
  • Provides host system with minimum possible latency by monitoring RDY
• Hardware reset input (RESET#)
  • Hardware method to reset the device for reading array data
• CMOS compatible inputs, CMOS compatible outputs

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Software Features

• Supports Common Flash Memory Interface (CFI)
• Software command set compatible with JEDEC 42.4 standard
• Data# Polling and toggle bits
• Provides a software method of detecting program and erase operation completion
• Erase Suspend/Resume
• Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Program Suspend/Resume
• Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation
• Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors
• Embedded Program algorithm automatically writes and verifies data at specified addresses

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Additional Features

• Program Operation
• Ability to perform synchronous and asynchronous program operation independent of burst control register setting

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