Distinctive Characteristics

• Single 1.8 Volt read, program and erase (1.65 to 1.95 volt)
• Manufactured on 0.13µm process technology
• VersatileIO™ (V_IO) Feature
• Device generates data output voltages and tolerates data input voltages as determined by the voltage on the V_IO pin
• 1.8V compatible I/O signals
• Contact factory for availability of 1.5V compatible I/O signals
• Simultaneous Read/Write operation
  • Data can be continuously read from one bank while executing erase/program functions in other bank
  • Zero latency between read and write operations
  • Four bank architecture: 8Mb/24Mb/24Mb/8Mb
• Programmable Burst Interface
• 2 Modes of Burst Read Operation
• Linear Burst: 8, 16, and 32 words with wrap-around
• Continuous Sequential Burst
• SecSi™(Secured Silicon) Sector region
  • Up to 128 words accessible through a command sequence
  • Up to 64 factory-locked words
  • Up to 64 customer-lockable words
• Sector Architecture
  • Sixteen 4 Kword sectors and one hundred twenty-six 32 Kword sectors
  • Banks A and D each contain eight 4 Kword sectors and fifteen 32 Kword sectors; Banks B and C each contain forty-eight 32 Kword sectors
  • Sixteen 4 Kword boot sectors: eight at the top of the address range and eight at the bottom of the address range
• Minimum 1 million erase cycle guarantee per sector
• 20-year data retention at 125°C
  • Reliable operation for the life of the system

Performance Characteristics

• Read access times at 66/54 MHz (C_L=30 pF)
  • Burst access times of 11/13.5 ns at industrial temperature range
  • Synchronous latency of 56/69 ns
  • Asynchronous random access times of 50/55 ns
    
• Power dissipation (typical values, C_L = 30 pF)
• Burst Mode Read: 10 mA
• Simultaneous Operation: 25 mA
• Program/Erase: 15 mA
• Standby mode: 0.2 µA

Hardware Features

• Handshaking: host monitors operations via RDY output
  • Provides host system with minimum possible latency by monitoring RDY
  • Reduced Wait-state handshaking option further reduces initial access cycles required for burst accesses beginning on even addresses
• Hardware reset input (RESET#)
  • Hardware method to reset the device for reading array data
• WP# input
• Write protect (WP#) function allows protection of the four highest and four lowest 4 kWord boot sectors, regardless of sector protect status
• Persistent Sector Protection
  • A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector
  • Sectors can be locked and unlocked in-system at VCC level
• Password Sector Protection
• A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
• ACC input: Acceleration function reduces programming time; all sectors locked when ACC = V_IL
• CMOS compatible inputs, CMOS compatible outputs
• Low V_CC write inhibit

Software Features

• Supports Common Flash Memory Interface (CFI)
• Software command set compatible with JEDEC 42.4 standards
  • Backwards compatible with Am29F and Am29LV families
• Data# Polling and Toggle Bits
  • Provides a software method of detecting program and erase operation completion
• Erase Suspend/Resume
• Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
• Unlock Bypass Program command
• Reduces overall programming time when issuing multiple program command sequences
• Burst Suspend/Resume
  • Suspends a burst operation to allow system use of the address and data bus, than resumes the burst at the previous state
    

PSRAM Features

• Power dissipation
• Operating: 25 mA
• Standby: 60 µA maximum

Return to Top