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Am42DL16x2D Product Overview
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memory and 2 Mbit (128 K x 16-Bit) Static RAM
General Description
Am29DL16xD Features
The Am29DL16xD family consists of 16 megabit, 3.0 Volt-only flash memory devices. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM programmers. The device is available with access times of 70 ns or 85 ns. The device is offered in a 69-ball FBGA package.
Distinctive Characteristics
| MCP Features |
Architectural Advantages |
Package Options |
Performance Characteristics |
Software Features |
Hardware Features |
SRAM Features |
|
MCP Features
- Power supply voltage of 2.7 to 3.3 volt
- High performance
- Access time as fast as 70 ns
- Operating Temperature
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Architectural Advantages
- Simultaneous Read/Write operations
- Data can be continuously read from one bank while executing erase/program functions in other bank
- Zero latency between read and write operations
- Secured Silicon (SecSi) Sector: Extra 64 KByte sector
- Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function
- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed
- Zero Power Operation
- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero
- Top or bottom boot block
- Manufactured on 0.23 µm process technology
- Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply flash standard
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Package Options
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Performance Characteristics
- High performance
- 70 ns access time
- Program time: 4 µs/word typical utilizing Accelerate function
- Ultra low power consumption (typical values)
- 2 mA active read current at 1 MHz
- 10 mA active read current at 5 MHz
- 200 nA in standby or automatic sleep mode
- Minimum 1 million write cycles guaranteed per sector
- 20 Year data retention at 125°C
- Reliable operation for the life of the system
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Software Features
- Data Management Software (DMS)
- AMD-supplied software manages data programming and erasing, enabling EEPROM emulation
- Eases sector erase limitations
- Supports Common Flash Memory Interface (CFI)
- Erase Suspend/Erase Resume
- Suspends erase operations to allow programming in same bank
- Data# Polling and Toggle Bits
- Provides a software method of detecting the status of program or erase cycles
- Unlock Bypass Program command
- Reduces overall programming time when issuing multiple program command sequences
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Hardware Features
- Any combination of sectors can be erased
- Ready/Busy# output (RY/BY#)
- Hardware method for detecting program or erase cycle completion
- Hardware reset pin (RESET#)
- Hardware method of resetting the internal state machine to reading array data
- WP#/ACC input pin
- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status
- Acceleration (ACC) function accelerates program timing
- Sector protection
- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector
- Temporary Sector Unprotect allows changing data in protected sectors in-system
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SRAM Features
- Power dissipation
- Operating: 20 mA maximum
- Standby: 10 µA maximum
- CE1#s and CE2s Chip Select
- Power down features using CE1#s and CE2s
- Data retention supply voltage: 1.5 to 3.3 volt
- Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
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