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Am41PDS3228D Product Overview
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Static RAM
General Description
Am29PDS322D Features
The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash memory organized as 2,097,152 words of 16 bits
each. The device is designed to be programmed in system with standard system 1.8 V Vcc supply. This
device can also be reprogrammed in standard EPROM programmers. The Am29PDS322D offers fast page access time of 40 ns with random access time of 100 ns (at 1.8 V to 2.2 V Vcc), allowing operation of high-speed microprocessors without wait states.
Distinctive Characteristics
| MCP Features |
SRAM Features |
Architectural Advantages |
Performance Characteristics |
Software Features |
Hardware Features |
MCP Features
- Power supply voltage of 1.8 to 2.2 volt
- High performance
- Access time as fast as 100 ns flash, 70 ns SRAM
- Package
- Operating Temperature
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SRAM Features
- Power dissipation
- Operating: 2 mA typical
- Standby: 0.5 µA typical
- CE1s# and CE2s Chip Select
- Power down features using CE1s# and CE2s
- Data retention supply voltage: 1.0 to 2.2 volt
- Byte data control: LB#s (DQ7-DQ0), UB#s (DQ15-DQ8)
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Flash Memory Features
Architectural Advantages
- Simultaneous Read/Write operations
- Data can be continuously read from one bank while executing erase/program functions in other bank
- Zero latency between read and write operations
- Page Mode Operation
- 4 word page allows fast asynchronous reads
- Dual Bank architecture
- One 4 Mbit bank and one 28 Mbit bank
- SecSi (Secured Silicon) Sector: Extra 64 KByte sector
- Factory locked and identifiable: 16 byte Electronic Serial Number available for factory secure, random ID; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data
- Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed
- Zero Power Operation
- Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero
- Package options
- Top or bottom boot block
- Manufactured on 0.23 µm process technology
- Compatible with JEDEC standards
- Pinout and software compatible with single-power-supply Flash standard
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Performance Characteristics
- High performance
- Random access time of 100 ns at 1.8 V to 2.2 V Vcc will be required as customers migrate downward in voltage
- Ultra low power consumption (typical values)
- 2.5 mA active read current at 1 MHz for initial page read
- 24 mA active read current at 10 MHz for initial page read
- 0.5 mA active read current at 10 MHz for intra-page read
- 1 mA active read current at 20 MHz for intra-page read
- 200 nA in standby or automatic sleep mode
- Minimum 1 million write cycles guaranteed per sector
- 20 Year data retention at 125°C
- Reliable operation for the life of the system
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Software Features
- Data Management Software (DMS)
- AMD-supplied software manages data programming, enabling EEPROM emulation
- Eases historical sector erase flash limitations
- Erase Suspend/Erase Resume
- Data# Polling and Toggle Bits
- Unlock Bypass Program command
- Reduces overall programming time when issuing multiple program command sequences
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Hardware Features
- Any combination of sectors can be erased
- Ready/Busy# output (RY/BY#)
- Hardware reset pin (RESET#)
- WP#/ACC input pin
- Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status
- Acceleration (ACC) function accelerates program timing
- Sector protection
- Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector
- Temporary Sector Unprotect allows changing data in protected sectors in-system
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