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GeodeLink™ architecture
- High-bandwidth interface unit that can handle up to 6Gbps of
data transfer
- Pipelining of multiple read and/or write requests from various
devices (up to 31 pipelined transactions)
- Peer-to-peer communication
- Power management
- 3.4W max. @ 333MHz (CRT)
- Block level gating
- Active hardware power management
- Software power management
- Low power I/O
GeodeLink™ control processor
- JTAG interface:
- ATPG, full scan, BIST on all arrays
- 1149.1 boundary scan compliant
- ICE interface
- Reset and clock control
- Designed for improved software debug methods and performance
analysis
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Memory
controller
- Integrated memory controller for low latency to CPU and on-chip
peripherals
- 64-bit wide SDRAM bus
Graphics processor
- High-performance 2D graphics controller
- Alpha BLT
- Integrated dot clock PLL
Display controller
- Supports up to 1600 x 1200 x 16 BPP and 1280 x 1024 x 24 BPP
@ 85Hz (CRT)
- Hardware-based VGA
- Hardware video up/down scaler
- Graphics/video alpha blending
- TFT or CRT interface
- Integrated CRT DACs
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