| Q: | What brand of pulse transformers does AMD recommend for this part?
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| A: | Magnetics from both Pulse Engineering and Halo have been used. The magnetics modules are 40 pin packages which contain isolation transformers (1:1 turns ratio) to support TX and RX for 4 ports.
Their part numbers are:
Pulse: PE68050
Halo: TG57-S020NX
If you are not interested in using the center taps, you can use standard dual 10Base-T isolation modules. You may decide to forego using the center taps based on your system's EMI performance. Two of these modules will fit within the footprint for the quad package so that you can layout one board with different stuffing options.
Halo: TG01-1006N2
Pulse: PE-68810
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| Q: | eIMR connection to a MAC: What additional components are required for a single eIMR and MAC application?
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| A: | If connecting the MAC to the eIMR's AUI port, the eIMR's AUI port will need to be configured in 'reversed mode'. This will switch the sense of the CI signals, so that the eIMR will drive CI+/- as outputs. The MAC's AUI signals can then connect directly to the eIMR's AUI ports without external circuitry as long as the MAC and the eIMR are on the same board. |
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| Q: | Changes to the TXD circuitry:
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| A: | FYI: The data sheet has the updated information and should be used as the reference. If you are designing from the FPS, the 100-Ohm resistor should be replaced with a 110-Ohm value, and the 50 pF capacitor should be removed. |
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| Q: | Terminating RXD:
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| A: | We have experimented with an alternate termination scheme on RXD+/-: we still terminate RXD in 100-Ohms, except that two 50-Ohm resistors (in series) decoupled to ground are used (capacitor is connected between the 2 resistors.) The capacitor may or may not be populated depending on EMI test results. We have found that capacitively coupling that structure to ground helps some designs meet the FCC requirements. For the eIMR eval board, I did not populate the caps. Either scheme will work for systems designed with the eIMR. |
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| Q: | Decoupling power and ground pins:
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| A: | The digital decoupling capacitors that are used on the eIMR evaluation board are different from those recommended in the AMD IEEE 802.3 Repeater Technical Manual (PID #17314B). The Manual (Section 6.2, pp 6-3) recommends using 0.1 uF decoupling caps between DVSS and DVDD pins, and 0.01 uF decoupling caps throughout the board. The evaluation board uses 0.01 uF decoupling caps between DVSS and DVDD pins, and 0.1 uF decoupling caps throughout the board. |
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| Q: | Layout of power and ground planes:
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| A: | The layout of the power and ground planes for the eIMR board will be different from prior IMR based systems since the eIMR has a single power plane internally. We do differentiate between analog and digital ground however, and we do isolate and filter the PLL pin separately. The PLL should be filtered with the low-pass filter network described below:
Pin 13 is dedicated to the receive PLL, and should be filtered separately with the low-pass filter network shown above. The 4.22 Ohm resistor and 22uF capacitor satisfy the relationship that RC>= 88. Therefore alternate values of R and C may be chosen that satisfy this relationship (where R is in Ohms, and C is in microfarads). Note that in order to minimize the voltage drop across the resistor, R should be kept below 10 Ohms.
As far as cutting the ground planes go, we cut both the ground and power planes beneath the transformers, to isolate the primary and secondary stages. The planes should be cut under the transformer package, leaving a gap of about 125 mils.
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| Q: | Regarding the SCLK, SI, SO pins on the management interface on the eIMR:
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| A: | SI should be tied high or low depending on whether or not they want the Auto Polarity function enabled or not.
SI - Tie it 'HIGH' if you want Receiver Auto Polarity Reversal disabled SI - Tie it 'LOW' if you want Receiver Auto Polarity Reversal enabled (resistor is optional) SCLK - Tie 'LOW' (resistor is optional) SO should be left unconnected since it is an output.
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| Q: | What to do with unused inputs SELi[1] and SELi[0]:
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| A: | They are shown pulled up through a resistor. In a Dual eIMR design, SEL0 of eIMR-1 would connect to SELi[0] of eIMR-2. SELi[1] would not be used. Question is if SELi[1] could be connected to Vdd without a pullup. You can tie it directly to Vdd. |
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| Q: | On the Reset to the eIMR, is it OK if I do not use a synchronous reset for the MAC (Ethernet Controller) and eIMR?
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| A: | You need to use a synchronous reset to the eIMRs and synch up the eIMRs (for multiple chips). However, reset does not need to be synchronized between the MAC and the eIMR. |
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| Q: | On your evaluation board, most of the pull up and pull down resistors that have been used are 1 Kohm. Is it Ok if I use higher value resistor as 10 Kohm instead?
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| A: | 10 K resistors should work fine. |
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| Q: | HIMIB to eIMR+ connection:
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| A: | Since one HIMIB device can collect the statistics for 8 TPs and 1 AUI port, 2 eIMR+ devices can be managed by 1 HIMIB. In this configuration, you will not be able to gather statistics for one of the AUI ports. However, the port remains fully functional and control of this port is provided via GET/SET commands. |
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| Q: | Partition algorithm for the AUI port:
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| A: | The AUI port will be partitioned according to the same conditions as the TP ports (frequency of collisions or duration of collisions). The reconnection algorithm can be programmed via the managementinterface, to use the standard (transmit or receive) or alternate (transmit only) algorithm. |
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| Q: | Do we tie unused inputs high or low?
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| A: | If you are using the eIMR in Internal arbitration mode, tie any unused inputs to the following state:
Tie High:
SELI[1:0]
ACK, COL
SI - if you want Receiver Auto Polarity Reversal disabled
AMODE - if you want to operate the AUI in Reverse mode
Tie Low:
DAT, JAM
SCLK
SI - if you want Receiver Auto Polarity Reversal enabled
AMODE - if you want to operate the AUI in normal mode
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| Q: | What do we think the max Icc would be with 2 10BASE-T ports transmitting?
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| A: | The per-enabled-port value for the power supply current is ~40 mA. Given that the total Icc with 4 ports transmitting is 300 mA, max Icc with 2 10BASE-T ports transmitting is about 300 - (2*40) = 220 mA. |
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| Q: | What is the most updated version of the eIMR demo board?
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| A: | Revision C dated 02/15/96 is the most updated schematics available. There are slight differences between it and the earlier versions that may be in circulation:
a. The AUI port was wired incorrectly (signal polarity) on rev A of the board
b. Crossover on the RJ45 connector was not done on rev A. Subsequent revisions corrected this
c. Used smaller decoupling caps for better high frequency response
d. Removed large 2Kv decoupling caps between chassis ground/power and digital ground/power.
e. Consolidated termination on RX
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| Q: | Is there an errata list on the 8 port hub schematics (dated 2/21)?
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| A: | On the page with the two eIMR controllers:
1. /ACK and /COL should have 1K pull-up resistors; DAT and JAM should have 1K pull- down resistors.
2. SELI1 on the second eIMR (U2) should be tied to Vdd , not to Vss.
Note: for the new revision of eIMR silicon (Rev B), the 220pF capacitor on the REXT pin is no longer needed. |
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| Q: | What things do I need to consider if I want the ability to hot swap our expansion units onto our main unit?
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| A: | I am assuming that you are using this in a stackable application, in which one of the units must be designated as the 'master' which sources the clock to the other units. If the 'master' unit gets swapped out, your stack will not work unless you have some mechanism in place to resolve the "master-slave" designation. |
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| Q: | Is buffering needed on the expansion bus for each eIMR?
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| A: | Each chip doesn't need to be buffered, but collectively the outputs of each board (DAT and JAM mainly) should be buffered.
If we need buffers for this, what kind of propagation delay can the bus handle? The propagation delay between boxes (port to port worst case) should be less than 100ns (1 BT) in order to ensure that the units operate as a single repeater. Since 100 ns is not a very large timing budget to work with when you consider the eIMR output delays, arbiter logic, etc., we suggest using the single-ended buffers. The differential buffers have large latencies associated with them, and may eat too much into the timing budget. You should select buffers which have about a typical 10-12 ns delay time (high to low output and low to high output). Note that you may have more or less time to play with here depending on how fast your arbiter resolves control, etc. Hence the typical number listed above is just a ball-park figure. You should do a timing analysis of your system to select the buffer that meets your needs.
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| Q: | There is a capacitor across the resistor input on the REXT pin. Is there any other functions besides stabilizing the ref voltage, can we omit it?
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| A: | You may omit it if you are using version B3 and higher. Earlier versions of the part needed this to filter the noise for the current reference. However, the part that is currently in production (B3) doesn't need it, and in fact functions incorrectly if this capacitor is left populated. |
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| Q: | Do you have the mechanical drawing for 100-pin device?
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| A: | The updated mechanicals and pin out of the 100-pin device is in the new data sheet on the web site.
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| Q: | What do we do with unused AUI inputs?
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| A: | The best thing to do is to tie DI+ to DI- and CI+ to CI-, as both pairs are differential and should cancel out any interference. |
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