PCI Express: An Overview
“Mime”

There has been a buzz about Peripheral Component Interconnect (PCI) Express (PCIE), since 2002, when the PCIE specification was finalized.

The most immediate need for PCIE is to replace the PCI bus. Introduced over a decade ago the PCI bus has become extremely overtaxed. In today's systems the PCI bus can't meet rising software and hardware demands.

Many have tried to relieve some stress on the PCI bus by introducing specialized buses. But these are patches applied over the real issue.

The best way to fix PCI-bus-caused bottlenecks is to switch to PCIE, which can meet today and tomorrow's software and hardware demands.

Bus Delays
PCIE Basics
Links, Lanes, Scalability, and Power
SLI™ Rendering and Auto Negotiation
Conclusion

Bus Delays
PCI-caused bottlenecks result from its shared bus topology.

The typical PCI bus has a maximum theoretical bandwidth of 133Mbps and is split between all devices using the bus. In an era of Gigabit Ethernet and RAID controllers, 133Mbps will act as a bottleneck whether or not PCI uses a shared bus topology.

Another consequence of the shared topology is that each device must contain some control logic, which carries out the process of bus arbitration. That is, PCI devices fight amongst themselves to figure out which is the bus master, controls the PCI bus, and can use it to talk to CPU and RAM via the Southbridge. Others have to sit and wait their turn.

Undoubtedly the PCI bus will remain in systems for some time to come. However, despite its widespread usage and long history, the days of the PCI bus directing general I/O traffic are coming to a close.

PCIE Basics
PCIE uses a point-to-point topology, which differs from the shared-bus topology of PCI. Its “smart” shared switch replaces PCI's shared host controller, so instead of sharing a central bandwidth pool, each PCIE device has its own dedicated link.

PCIE's higher bandwidth means you can integrate the switch into the Southbridge , the Northbridge, or both. Effectively, the switch works like a network router, rapidly switching between connections to conjure the illusion that each device enjoys exclusive access.

Similar to a network router, PCIE works on a packet-based model. It also localizes decision making at the shared switch. When combined, these innovations yield new possibilities, such as improved Quality of Service (QoS), which gives real-time applications higher priority and background tasks lower priority. Other innovations include packet retries and the hot swapping of devices. And since the switch decides which connections to make and when, PCIE reduces demands on devices.

PCIE employs a high-speed serial methodology. While a parallel bus sends chunks of data side by side, a serial bus sends one chunk after another. At the same clock speed, a parallel bus will provide more bandwidth than a serial bus.

However, there are problems with raising to new levels the clock speed of a parallel bus – the greater the speed, the more sensitive to “noise” it becomes. In other words, parallel buses suffer from more crosstalk issues, which occur when signals traveling across the bus bleed into each other. As addressing this problem by widening the bus is an expensive option, serial buses like PCIE are growing in popularity.

Even though PCIE is designed in part as a replacement for PCI, it enjoys backward compatibility with PCI – in terms of software, not hardware.

Links, Lanes, Scalability, and Power
An especially useful feature of PCIE is that it scales up with the addition of extra “lanes.” A connection from the shared switch to a PCIE device is a “link,” and each link comprises at least one lane. (Currently PCIE runs at 2.5Ghz, but will be ramped up to 10GHz in the future. The maximum theoretical bandwidth of a PCIE lane is 2.5Gbps.) A PCIE link with only one lane is an x1 link – add another lane, it becomes an x2 link, and so on. Each lane is bidirectional, can send and receive data simultaneously, and can provide 250MBps of bandwidth in both directions.

The PCIE specification defines x1, x2, x4, x8, x12, x16, and x32 link widths. The x1 PCIE link was designed to replace the PCI bus. The x16 link is intended to replace AGP*. The x32 link remains unimplemented.

PCIE's potential bandwidth will change the design of the typical PC and encourage the creation of more bandwidth-intensive applications.

* AGP, which was designed to take some of the load off PCI, is similar to PCI and shares some of the same problems – however, it does have some distinctive features. AGP was created specifically for graphics cards and designed to share a portion of main memory to store rendering data, rather than having to load the data into the onboard video memory. New generation video cards sometimes require two separate power connectors, because they outstrip AGP's energy supply capabilities. While the AGP bus can supply a maximum of 25 watts, PCIE can supply 60 watts now and up to 75 watts in the future, thus cutting the need for extra cables.

Originally, SLI split the odd and even lines displayed on a monitor – one video card rendered the even lines, another the odd lines, with little attention to the detail of a rendering. “Old” SLI required an external pass-through cable and an internal ribbon cable.

“New” SLI – renamed Scalable Link Interface rendering – attends to the detail of a rendering, rather than splitting the odd and even lines. It requires no pass-through cable, and a small PCB with two small connectors joins the two video cards. The video card connected to the monitor is the master, the other the slave.

High-end SLI will no doubt remain a niche product, since buying two high-end video cards and an SLI capable motherboard is an expensive proposition. But for those dead set on in-depth gaming and real 3D rendering, it will be a must have.

High-end SLI will benefit from PCIE's ability to auto negotiate mismatched slot widths and link widths. At system start-up, a PCIE device negotiates with the shared switch to find the maximum available link width. If the slot and the link width are the same, the negotiation is simple.

But you also can use an x8 PCIE device in an x16 PCIE slot. In this negotiation, the PCIE device will tell the shared switch it is an x8 device. The shared switch will switch off the x16 connector's extra pins. Similarly, link width – the connection from the PCIE slot to the shared switch – takes part in the negotiation. If an x16 PCIE device is used in an x16 PCIE slot, but the link width is x8, the shared switch will switch off the extra wires and pins in the slot and device to make it work as an x8 device.

Conclusion
As PCIE replaces both PCI and AGP, computers will:

• Become tidier
• Gain a high-speed, intelligent, scalable backbone for I/O traffic
• Use lower pin counts and cost less, while providing unprecedented bandwidth
• Benefit from packet-based usage and localized decision making
• Enjoy backward compatibility with PCI
• Be scalable to cope with future needs, and thus protect users' investments

PCIE compatible chipsets are available from VIA, NVIDIA, ATI, and others. And many motherboard manufacturers are using them in their AMD Athlon™ 64 processor compatible motherboards.

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