Key Architectural Features of the AMD Athlon™ MP Processor Include:
Smart MP technology for smarter multiprocessing:
- Dual point-to-point, high-speed system buses
- Innovative bus snooping capability
- Optimized MOESI cache coherency protocol
QuantiSpeed™ architecture for enhanced performance:
- Nine-issue superpipelined, superscalar x86 processor microarchitecture designed for high performance
- Multiple parallel x86 instruction decoders
- Three out-of-order, superscalar, fully pipelined floating point execution units, which execute x87 (floating point), MMX™ and 3DNow!™ instructions
- Three out-of-order, superscalar, pipelined integer units
- Three out-of-order, superscalar, pipelined address calculation units
- 72-entry instruction control unit
- Advanced hardware data prefetch
- Exclusive and speculative Translation Look-aside Buffers
- Advanced dynamic branch prediction
3DNow!™ Professional technology for leading-edge 3D operation:
- 21 original 3DNow!™ instructions enabling superscalar SIMD
- 19 additional instructions to enable improved integer math calculations for speech or video encoding and improved data movement for Internet plug-ins and other streaming applications
- 5 DSP instructions to improve soft modem, soft ADSL, Dolby Digital surround sound, and MP3 applications
- 52 SSE instructions with SIMD integer and floating point additions offer excellent compatibility with Intel’s SSE technology
- Compatible with Windows® XP, Windows 2000, Windows ME, and Windows 98 operating systems
266MHz AMD Athlon™ MP processor system bus enables excellent system bandwidth for data movement-intensive applications:
- Source synchronous clocking (clock forwarding) technology
- Support for 8-bit ECC for data bus integrity
- Peak data rate of 2.1GB/s
- Multiprocessing support: point-to-point topology, with number of processors in SMP systems determined by chipset implementation
- Support for 24 outstanding transactions per processor
The AMD Athlon™ MP processor with performance-enhancing cache memory features 64K instruction and 64K data cache for a total of 128K L1 cache. 512K of integrated, on-chip L2 cache for a total of 640K full-speed, on-chip cache.
Socket A infrastructure designs are based on high-performance platforms and are supported by a full line of optimized infrastructure solutions (chipsets, motherboards, BIOS):
- Available in Pin Grid Array (PGA) for mounting in a socketed infrastructure
- Electrical interface compatible with 266MHz AMD Athlon MP system buses, based on Alpha™ EV6 bus protocol
Die size: approximately 54.3 million transistors on 101mm2. Manufactured
using AMD's state-of-the-art 0.13-micron copper process technology at AMD's
Fab 30 wafer fabrication facility in Dresden, Germany.
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