Nine-issue superpipelined, superscalar x86 processor microarchitecture designed for high performance
Multiple parallel x86 instruction decoders
Three out-of-order, superscalar, fully pipelined floating point execution units, which execute x87 (floating point), MMX™ and 3DNow!™ instructions
Three out-of-order, superscalar, pipelined integer units
Three out-of-order, superscalar, pipelined address calculation units
72-entry instruction control unit
Advanced hardware data prefetch
Exclusive and speculative Translation Look-aside Buffers
Advanced dynamic branch prediction

3DNow!™ Professional technology for leading-edge 3D operation

21 original 3DNow!™ instructions—the first technology enabling superscalar SIMD
19 additional instructions to enable improved integer math calculations for speech or video encoding and improved data movement for Internet plug-ins and other streaming applications
5 DSP instructions to improve soft modem, soft ADSL, Dolby Digital surround sound, and MP3 applications
52 SSE instructions with SIMD integer and floating point additions offer excellent compatibility with Intel’s SSE technology
Compatible with Windows® XP, Windows 2000, Windows ME, and Windows 98 operating systems

400 MHz, 333MHz and 266Mhz AMD Athlon™ XP processor system bus enables excellent system bandwidth for data movement-intensive applications

Source synchronous clocking (clock forwarding) technology
Peak data rate of 3.2GB/s
Support for 64-bit bi-directional data

The AMD Athlon™ XP processor with performance-enhancing cache memory features 64K instruction and 64K data cache for a total of 128K L1 cache. 512K of integrated, on-chip L2 cache for a total of 640K full-speed, on-chip cache.

Socket A infrastructure designs are based on high-performance platforms and are supported by a full line of optimized infrastructure solutions (chipsets, motherboards, BIOS).

Available in Pin Grid Array (PGA) for mounting in a socketed infrastructure
Electrical interface compatible with 333MHz AMD Athlon XP system buses, based on Alpha EV6™ bus protocol

Die size: approximately 54.3 million transistors on 101mm². Manufactured using AMD's state-of-the-art 0.13-micron copper process technology at AMD's Fab 30 wafer fabrication facility in Dresden, Germany.