Introduction to the Versal Adaptive SoC AI Engine and to its Programming Model
Abstract
The Versal adaptive SoC is the latest generation technology in the Xilinx (now part of AMD) product line. Versal devices feature: AI Engine (AIE), Programmable Logic (Adaptable Engine), and Processing System (Scalar Engine). These three Engines, tightly-coupled with a network-on-chip (NoC), constitute a truly heterogeneous system in a single chip.
The AIE, a new type of compute element, is a tiled array of very long instruction word (VLIW) and Single Instruction Multiple Data (SIMD) processing elements that provides high compute density, helping overcome the decline of Moore’s law. At CES 2023, Lisa Su (AMD CEO) announced the integration of AIE on Ryzen 7040 AMD processors. More information about AIE here.
This tutorial will primarily focus on the Adaptable Intelligent Engine; however, we will briefly describe the Versal architecture. This tutorial lays the foundations for understanding the capabilities of the Adaptable Intelligent Engine, its programming model, data movement and computation model (data flow architecture). Also, the hands-on session will allow attendees to explore the tools with fully functional examples.
Agenda
The times in this agenda are tentative.
| Time (MST) | Topic |
|---|---|
| 1:00 PM – 2:50 PM | Brief Overview of the Versal Adaptive SoC Architecture AI Engine Value Proposition VCK5000 Platform Versal AI Engine Memory and Data Movement Introduction to the Versal AI Engine Architecture Get connected to AWS and start hands-on: vadd lab |
| 2:50 PM – 3:10 PM | Coffee Break |
| 3:10 PM – 5:00 PM | Scalar and Vector Data Types AI Engine APIs Window Data APIs Hands-on: matrix mult lab Next steps & HACCs |
Reference material can be found here: https://xilinx.github.io/xup_aie_training/
Prerequisites
Some basic FPGA awareness would be an advantage, but is not required, although participants should have some knowledge of parallel processing concepts and/or parallel hardware. Familiarity with the C++ programming language would be an advantage.
AMD will provide remote access to cloud instances which will be enabled with tools and devices. Attendees must have their own laptop with reasonable screen size to effectively use the required software (Tablet, and Netbook type devices are not suitable).
About Us
Instructors’ affiliation: AMD University Program, at Advanced Micro Devices, Inc. (AMD)
Dr. Mario Ruiz
Mario is a member of technical staff in AMD University Program. As part of this role, he delivers training workshops for academics on the latest AMD tools and technologies. Mario completed his PhD in the Autonomous University of Madrid, which was focused on exploring High Level Synthesis tools in the context of networking.
Contact Us
You can reach us at aup@amd.com
Registration
2-6 March, 2024
8:30 AM – 5:00 PM (GST)
In Person: Check the HPCA 2024 site for more information. https://www.hpca-conf.org/2024/program/workshops-tutorials.php