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课程信息
- 描述
通过本课程，教授可以了解使用 Vivado HLS 开发数字系统所需的高层次综合设计方法。
- 适应水平
入门
- 时长
2 天
- 培训对象
熟悉 AMD FPGA 技术并希望利用高层次综合技术快速掌握系统设计的教授。
- 预先要求
拥有使用 AMD FPGA 进行系统级设计的相关经验
拥有 Vivado Design Suite 基本使用经验
Good understanding of C programming
可掌握的技能
After completing this workshop, you will be able to:
- Understand high-level synthesis flow of Vivado HLS
- 应用指令以优化设计性能
- Perform system-level integration of blocks generated by the Vivado HLS tool
课程概述
第 1 天：
- 介绍 HLS
- Using Vivado HLS
- 实验课 1：创建项目并了解报告
- Experience a basic design flow of Vivado HLS and review generated output.
- Experience a basic design flow of Vivado HLS and review generated output.
- Improving Performance
- 实验课 2：通过流水线设计优化性能
- Use pipelining technique to improve performance.
- Use pipelining technique to improve performance.
- 数据类型
第 2 天：
- Optimizing for Area and Resources
- 实验课 3：提高区域和资源利用率
- Use directives to optimize resource sharing.
- Use directives to optimize resource sharing.
- Handling Block- and Port-Level Protocols
- Coding Considerations
- Creating a Processor System
- 实验课 4：设计音频系统
- Use IP-XACT export capability of Vivado HLS to generate an IP and integrate the generated core in an embedded system developed using IP Integrator.
- 实验课指示信息和源文件
- 演示文稿 (PDF)