System Design Flow on Zynq using Vivado

可掌握的技能

After completing this workshop, you will be able to:

• 通过 AMD 设计约束条件实现性能
• 使用 Vivado 和 IP Integrator 快速构建以 ZedBoard 上的 Zynq ARM 处理器为目标的嵌入式系统 
• 利用 AMD 提供的外设扩展硬件系统
• 创建自定义外设并将其添加到系统中
• Debug a design using Vivado hardware analyzer
• Use Vivado HLS to generate an IP-XACT compliant hardware accelerator

课程概述

第 1 天：

• 7-Series Architecture Overview
  
  
• Vivado 设计流程
  
  
• 实验课 1：创建 HDL 设计
  • Use Vivado IDE to create a simple HDL design.Simulate the design using the XSIM HDL simulator available in Vivado design suite.Generate the bitstream and verify in hardware.
     
• AMD 设计约束条件
  
  
• 实验课 2：AMD 设计约束条件
  • Create a project with I/O Planning type, enter pin locations, and export it to the rtl.Then create the timing constraints and perform the timing analysis.
     
• IP Integrator and Embedded System Design Flow
  
  
• 实验课 3：使用 IP Integrator 创建处理器系统
  • Create a simple ARM Cortex-A9 based processor design targeting the ZedBoard using IP Integrator.

第 2 天：

• Embedded System Design with Custom IP
  
  
• 实验课 4：创建和添加自己的定制 IP
  • Use the Manage IP feature of Vivado to create a custom IP and extend the system with the custom peripheral.编写访问外设的基本 C 应用。
     
• System Debugging using Vivado Logic Analyzer and SDK
  
  
• 实验课 5：使用 Vivado 逻辑分析器核心进行调试
  • Insert various Vivado Logic Analyzer cores to debug/analyze system behavior.
     
• Profiling and Performance Improvement
  
  
• Introduction to High-Level Synthesis with Vivado HLS
  
  
• Improving Performance and Resource Utilization
  
  
• Creating an Accelerator
  
  
• 实验课 6：使用加速器创建处理器系统
  • Profile an application performing a function both in software and hardware.Create an accelerator in Vivado HLS.Use the generated accelerator to build a complete system.