SmartLynq+ Module

发布者: AMD

The SmartLynq+ module is built for high-speed debug and trace, primarily targeting designs using Versal™ platform. The SmartLynq+ modules provide up to 28X faster Linux download time via high-speed debug port (HSDP) and much-improved configuration throughput performance over previous debug products to accelerate the development cycle. The SmartLynq+ module supports both serial and parallel trace, with up to 14GB of trace memory to capture a detailed picture of design execution history. The SmartLynq+ module is fully compatible with Versal™ ACAP evaluation boards so that users have full visibility to the Versal architecture, including AI Engines, programmable network on chip (NoC), DDR memory controller, and 100G multirate Ethernet cores. The SmartLynq+ module features various host and target connectivity options, making it the most flexible debug product in the portfolio. Software packages, with Python for the integrated debugger, provide maximum flexibility by enabling remote access and sharing.