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64-bit Initiator/Target for PCI-X™ & 32- and 64-bit Initiator/Target for PCI™

发布者: AMD

产品编号:
- EF-DI-PCIX64-VE-SITE
设计工具支持: ISE Design Suite
器件支持: Virtex FPGAs, Artix 7, Spartan 6, Kintex 7, Virtex 7, Spartan 3E, Spartan 3, Spartan 3AN, Spartan IIE, Spartan II, Virtex E, Virtex 5, Virtex II Pro, Virtex II, Virtex 4

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Overview
Documentation

Product Description

This bundle includes the 64-bit Initiator / Target for PCI-X™ and both the 64-bit and 32-bit Initiator / Target for PCI™ and enables designers to build a variety of customized 64-bit and 32-bit systems running at speeds up to 133 MHz with performance approaching 1066 MBytes per second. It provides a programmable solution with customizable back-end functionality. PCI™ is widely deployed in systems, industrial computers, communication switches, routers, and instrumentation. It solves a wide range of compatibility challenges and performance limitations that were encountered with older ISE™ and VME standards.

DO-DI-PCI-VE PCI Configurations
FPGA Device	Performance	IP Overviews	Technical Documents
Kintex™ 7, Artix™ 7, Zynq™ 7000, Virtex™ 5, Virtex 4, Virtex II Pro, Spartan™ 6 (33 Mhz only), Spartan 3 generation	64-bit 66 MHz	Standalone	Data sheet
Kintex 7, Artix 7, Zynq 7000, Virtex 5, Virtex 4, Virtex II Pro, Spartan 6 (33 Mhz only), Spartan 3 generation	32-bit 66 MHz	Standalone	Data sheet
Virtex 4, Virtex II Pro, Spartan 3 generation	32-bit 66 MHz or 33 MHz	OPB/PLB*	Data sheet
Virtex 5, Virtex 4, Spartan 3 generation	32-bit 33 MHz	PLB v4.6*	Data sheet
DO-DI-PCI-VE PCI-X Configurations
FPGA Device	Performance	IP	Technical Documents
Virtex 5, Virtex 4, Virtex II Pro	64-bit 133 MHz		Data sheet

Please refer to the individual data sheet for each core for part and package support information. To generate the Core Generator™ license key for the respective product, please link to the IP Overview page and select access lounge on the left hand side.

Key Features and Benefits

Fully PCI-X 2.0 Mode1 compliant core, 64-bit, 133/66 MHz interface with 3.3 V operation
Customizable, programmable, single-chip solution
Predefined implementation for predictable timing
Incorporates Smart-IP™ Technology
Fully PCI 3.0 core compliant, 64/32-bit, 33 MHz PCI initiator and target interface
3.3v PCI-X operation at 33-133 MHz, 3.3V PCI operation at 0-33 MHz
Fully verified design tested with AMD proprietary testbench
Optional dual-port FIFOs may be added for maximum burst performance
Integrated extended capabilities - PCI-X Capability Item, Power Management Capability Item, Message Signalled Interrupt Capability Item
Available for configuration and download on the web

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

XAPP456 - Custom PCI Timing Budgets for Spartan-3 Generation FPGAs

The PCI™ Local Bus Specification, Revision 3.0 (“the PCI specification”), defines two timing budgets. One timing budget is for use with 33 MHz operation, and the other timing budget is for use with 66 MHz operation. These two timing budgets define the I/O timing parameters for compliant 33 MHz and 66 MHz components

View Application Note

DS208 - LogiCORE IP Initiator/Target v5 and v6 for PCI-X Data Sheet (DS208) (v11.0)

The LogiCORE™ IP Initiator/Target v5 and v6 for PCI-X™ core interface is a pre-implemented and fully tested module for AMD FPGAs.

View Product Guide

_{Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.}

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64-bit Initiator/Target for PCI-X™ & 32- and 64-bit Initiator/Target for PCI™

Product Description

Key Features and Benefits

Related Products

Documentation