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Versal™ Adaptive SoC Integrated Block for PCI Express®

发布者: AMD

The Versal™ adaptive SoC Integrated Block for PCI Express® is a building block IP for high-bandwidth, scalable, and reliable serial interconnect based on the PCI Express specification.

设计工具支持: Vivado Software
捆绑产品: Vivado Software
许可: End User License Agreement
器件支持: Versal AI Core, Versal AI Edge, Versal HBM, Versal Premium, Versal Prime

Overview
Documentation

Product Description

The Versal™ adaptive SoC Integrated Block for PCI Express® is a building block IP for high-bandwidth, scalable, and reliable serial interconnect based on the PCI Express specification. Designs that configure an available programmable logic integrated block for PCI Express (PL PCIE) can realize a specific implementation of the PCI Express Base Revision 4.0 (PL PCIE4) or the PCI Express Base Revision 5.0 (PL PCIE5).

Key Features and Benefits

Versal devices with PL PCIE5 support:
- Maximum link width based on available GTYP in the selected device/package.
- Gen1 (2.5 GT/s/lane), Gen2 (5.0 GT/s/lane), Gen3 (8.0 GT/s/lane) rates at up to x16 link widths
- Gen4 (16.0 GT/s/lane) rate at up to x8 link widths
- Gen5 (32.0 GT/s/lane) rate at up to x4 link widths
Versal devices with PL PCIE4 support:
- Maximum link width based on available GTY in the selected device/package
- Gen1 (2.5 GT/s/lane), Gen2 (5.0 GT/s/lane), Gen3 (8.0 GT/s/lane) rates at up to x16 link widths
- Gen4 (16.0 GT/s/lane) rate at up to x8 link widths
Endpoint, Root Port, Switch Port Upstream, Switch Port Downstream, and Legacy Endpoint modes
AXI4-Stream transaction-layer interfaces to programmable logic (RQ/RC/CQ/CC)
Advanced error reporting (AER) and end-to-end CRC (ECRC)
One virtual channel, eight traffic classes
Single-root I/O virtualization (SR-IOV)
MSI-X, MSI, and INTx interrupt support

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

ACAP-PCIE - Designing with the Versal Adaptive SoC: PCI Express Systems (ACAP-PCIE) (v1.0)

This course introduces the features and capabilities of the PCIe® and Cache Coherent Interconnect blocks in the AMD Versal™ adaptive SoC architecture. Learn how to implement a Versal device PCI Express® solution in custom applications to improve time to market.

View Customer Training

PG343 - Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) (v1.0)

Provides detailed information about AMD Versal Integrated Block for PCI Express core.

View Product Guide

_{Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.}

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Versal™ Adaptive SoC Integrated Block for PCI Express®

Product Description

Key Features and Benefits

Documentation