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System Monitor Wizard

发布者: AMD

The LogiCORE™ IP System Monitor Wizard for Virtex™ 6 and Virtex 5 FPGAs automates the task of instantiating the System Monitor block in your HDL design.

设计工具支持: ISE Design Suite
捆绑产品: ISE Design Suite
许可: End User License Agreement
器件支持: Virtex 6, Virtex 5

Overview
Documentation
Supported Tool Version

Product Description

The LogiCORE™ IP System Monitor Wizard for Virtex™ 6 and Virtex 5 FPGAs automates the task of instantiating the System Monitor block in your HDL design. The counterpart of the System Monitor block in Virtex 6 and Virtex 5 FPGAs in the 7 Series FPGAs is the XADC block, which can be configured using the LogiCORE IP XADC Wizard. The customization GUIs of both wizards make it easy for the user to configure these hardware blocks for the desired mode of operation.

Key Features and Benefits

Easy configuration of required modes and parameters
Simple interface for channel selection and configuration
Ability to select/deselect alarm outputs and to set alarm limits
Calculates all parameter and register values

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

DS608 - LogiCORE IP System Monitor Wizard v2.1 Data Sheet (v2.1)

The LogiCORE™ IP System Monitor Wizard simplifies the instantiation of the System Monitor into the design in Virtex™ 5 and Virtex 6 FPGAs. The Wizard creates an HDL file (Verilog® or VHDL) that instantiates and configures the System Monitor to customer requirements.

View Data Sheet

UG247 - LogiCORE IP System Monitor Wizard v2.1 Getting Started Guide (UG247) (v2.1)

This getting started guide describes the function and operation of the AMD LogiCORE IP System Monitor Wizard in the Virtex 5 LX/LXT/SXT sub-families, Virtex 6 LXT/SXT/HXT sub-families, lower-power VIrtex 6 devices, and Virtex 5Q and Virtex 6Q defense grade devices.

View U