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Serial RapidIO LogiCORE™ IP

por: AMD

The LogiCORE™ RapidIO Logical (I/O) and Transport Layer Interface is optimized for Virtex™ II and Virtex II Pro series FPGAs and is compliant with Logical Input/Output and Common Transport Specification 1.2.

Part Number:
- EF-DI-RIO-SITE
Design Tools Support: ISE Design Suite
Licencia: Core License Agreement
Device Support: Virtex 4, Virtex 5, Virtex 6

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Overview
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Supported Tool Version

Product Description

LogiCORE™ IP Serial RapidIO v5.6 – SRIO Gen 1.3 (with extensions for Gen 2 -5G line rate) Support.
For the Serial RapidIO Gen 2 LogiCORE IP, please click here.

The LogiCORE IP Serial RapidIO Endpoint solution, designed to RapidIO Gen 1.3 specification with Gen 2 -5G line rate support, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) AND Transport Layer core. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.

The RapidIO Logical (I/O) and Transport Layer core and the RapidIO Physical Layer core, provide a complete Serial RapidIO protocol stack. Additionally, a highly optimized and configurable buffer design is included with these cores to implement a Serial RapidIO endpoint. While a modular IP design approach provides flexibility to enable ease of customization, the AMD tool chain automates generation of the serial endpoint on an FPGA by using these building block IP cores through a configurable and easy-to-use graphical user interface.

Key Features and Benefits

1x & 4x Serial PHY - Supports Virtex™ 6 LXT/SXT/HXT, Spartan™ 6 LXT, Virtex 5 LXT/SXT/FXT, and Virtex 4 FX FPGAs
1x & 4x Serial PHY - Supports 1.25, 2.5, 3.125, 5.0 Gpbs line speed
1x & 4x Serial PHY - 64-bit internal data path
Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
Doorbell and message support
Support for priority based re-transmit suppression
Independently configurable TX and RX buffer depths

Resource Utilization

Resource Utilization for Serial RapidIO Gen2

Documentation

ISE Release Notes

This document contains a listing of release note tables, one for each IP core.

View Release Note

PG007 - Serial RapidIO Gen2 Endpoint v4.1 Product Guide (PG007) (v4.1)

The Serial RapidIO Gen2 Endpoint Solution (SRIO Gen2 Endpoint) comprises a highly flexible and optimized Serial RapidIO Gen2 Physical Layer and a Serial RapidIO Gen2 Logical (I/O) and Transport Layer.

View Product Guide

Serial RapidIO Supported Tool Version

Hardware Evaluation Time Out Period * : ~ 8 hrs

LogiCORE™	Version	Software Support	Supported Device Families
RapidIO Physical Layer Interface Core Gen 1	v5.6	ISE™ 13.1	Virtex™ 6 HXT / LXT / SXT Virtex 5 FXT / SXT / LXT Virtex 4 FX Spartan™ 6 LXT

_{Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.}

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Serial RapidIO LogiCORE™ IP

Product Description

Key Features and Benefits

Resource Utilization

Related Product

Documentation

ISE Release Notes

PG007 - Serial RapidIO Gen2 Endpoint v4.1 Product Guide (PG007) (v4.1)

Serial RapidIO Supported Tool Version

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