教程和实验课练习

AUP 开发了与 AUP 支持的设计板配套使用的教程和实验练习。The laboratory material is targeted for use in a introductory Digital Design course where professors want to include FPGA technology in the course to validate the learned principles through creating designs using Vivado.

编写本教程的目的是让用户（学生）了解使用 Vivado Design Suite 在 AMD 可编程器件中进行数字设计的相关流程。实验练习包括基本的 HDL 建模原理和问题陈述。 教授可以按需布置每个实验文件中提供的练习。 教授也可以单独请求访问实验练习的相应源代码。 考虑到一个学期中的期中和期末考试需要几周的时间，练习的数量足以为一个学期的课程提供足够的资料。

教授们可获取每项练习的完整源文档。 有兴趣获得完整源文档的教授，请发送电子邮件至 AUP，在电子邮件正文中注明语言 (Verilog/VHDL)，并提供完整的标题、电子邮件地址和大学地址。“如何创建自己的 IPI 块”指南将指导您创建定制 IPI 块，然后在未来的设计中使用它。  

Supporting Material

Master XDC File Basys3.xdc Nexys4DDR.xdc Nexys4.xdc
参考手册 Basys3_rm.pdf Nexys4DDR_rm.pdf Nexys4_rm.pdf
示意图 Basys3_sch.pdf Nexys4DDR_sch.pdf Nexys4_sch.pdf

Labs Material


标题		 Verilog VHDL
2015x 2013x 2015x 2013x
PDF Source PDF Source PDF Source PDF Source
Vivado Tutorial 教程 教程 教程 教程 教程 教程 教程 教程
Lab1 - Modeling Concepts Lab1 Lab1 Lab1 Lab1 Lab1 Lab1 Lab1 Lab1
Lab2 - Numbering Systems Lab2 Lab2 Lab2 Lab2 Lab2 Lab2 Lab2 Lab2
Lab3 - Multi-Output Circuits Lab3 Lab3 Lab3 Lab3 Lab3 Lab3 Lab3 Lab3
Lab4 - Tasks, Functions, and Testbench Lab4 Lab4 Lab4 Lab4 Lab4 Lab4 Lab4 Lab4
Lab5 - Modeling Latches and Flip-Flops Lab5 Lab5 Lab5 Not required Lab5 Lab5 Lab5 Not required
Lab6 - Modeling Registers and Counters Lab6 Not required Lab6 Not required Lab6 Not required Lab6 Not required
Lab7 - Behavioral Modeling and Timing Constraints Lab7 Not required Lab7 Not required Lab7 Not required Lab7 Not required
Lab8 - Architectural Wizard and IP Catalog Lab8 Not required Lab8 Not required Lab8 Not required Lab8 Not required
Lab9 - Counters, Timers, and Real-Time Clock Lab9 Not required Lab9 Not required Lab9 Not required Lab9 Not required
Lab10 - Finite State Machines Lab10 Not required Lab10 Not required Lab10 Not required Lab10 Not required
Lab11 - Sequential System Design using ASM Charts Lab11 Not required Lab11 Not required Lab11 Not required Lab11 Not required

Vivado Supported Boards