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AXI Register Slice

发布者: AMD

The AXI Register Slice may be used on selected pathways between AXI endpoints, crossbars, and interconnects in order to break critical timing paths and achieve higher clock frequencies.

设计工具支持: Vivado Software
捆绑产品: Vivado Software
许可: End User License Agreement
器件支持: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Versal AI Core, Versal Prime, Virtex 7, Virtex UltraScale, Zynq 7000

Overview
Documentation
Supported Tool Version

Product Description

The AXI Register Slice may be used on selected pathways between AXI endpoints, crossbars, and interconnects in order to break critical timing paths and achieve higher clock frequencies. For each Register Slice instance, you can selectively enable pipelining on any of the five AXI channels. Placement constraints make the AXI Register Slice very useful for crossing SLR boundaries. Use the Register Slice directly in your design, or between switches, like AXI Interconnect.

Key Features and Benefits

Ideal for breaking up a critical timing path
Ideal for crossing SLR boundaries
Supports AXI4, AXI3, and AXI4-Lite
Fully configurable to match your AXI port widths
Set each of the five channels independently, for optimal latency and performance characteristics
Timing driven mode allows the implementation tools to pipeline as much, or as little, as needed in order to meet timing
Propagates AXI traffic with no loss in performance
Multiple available modes, like Bypass, Lightweight, Full, SLR Crossing, and Multi-SLR Crossing

Resource Utilization

AXI Register Slice Resource Utilization

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG373 - AXI Register Slice LogiCORE IP Product Guide (PG373) (v2.1)

Describes the AXI Register Slice IP.

View Product Guide axi-register-slice.html