发布者: AMD
AMD provides the ability to configure the FPGA Built-in Endpoint Block for PCIe® available in Virtex™ 5 FPGAs.
AMD provides the ability to configure the FPGA Built-in Endpoint Block for PCIe® available in Virtex™ 5 FPGAs. In addition to configuring the block, the core also provides all of the supplemental logic required to deliver a complete Endpoint solution for PCIe. This AMD Endpoint Block Plus Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other AMD connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE™ users can request a license file by clicking the “Get License” button on this page.
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| Virtex™ 5 Endpoint Block Plus Wrapper for PCE Express® (PCIe®) | v1.15 | ISE™ 13.2 | Virtex 5 TXT / SXT / LXT (-1, -2, -3) |
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.