Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
发布者: AMD
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite provides an interface for asynchronous serial data transfer.
The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance Microcontroller Bus Architecture) AXI (Advanced eXtensible Interface) and provides the controller interface for asynchronous serial data transfer. This soft IP core is designed to connect via an AXI4-Lite interface. The AXI UART 16550 described in this document incorporates features described in the National Semiconductor PC16550D UART with FIFOs Data Sheet.
The National Semiconductor PC16550D data sheet is referenced throughout this document and should be used as the authoritative specification. Differences between the National Semiconductor PC16550D and the AXI UART 16550 data sheet are highlighted in the Specification Exceptions section.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI UART 16550 |
v2.0 | AXI4-Lite | Vivado™ 2016.3 | Kintex™ 7 UltraScale+™ Virtex™ 7 UltraScale+ Zynq™ 7000 UltraScale+ Kintex 7 UltraScale™ Virtex 7 UltraScale Artix™ 7 Kintex 7 Virtex 7 Zynq 7000 |
AXI UART 16550 |
v1.01a | AXI4-Lite | EDK™ 14.2 | Zynq 7000 Artix 7 Kintex 7 Virtex 7 Virtex 6 HXT / SXT / LXT Spartan™ 6 LX / LX |
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