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Course Information
- Description
 This course provides professors with an introduction to the partial reconfiguration design flow in AMD FPGAs using Vivado™ design tools.
- Level
 Intermediate
- Duration
 2 Days
- Who Should Attend
 Professors who want to use partial reconfiguration technology and design flow in their research
- Pre-requisites
 Conceptual understanding of AMD FPGA and hardware design
Experience with Vivado and SDK (recommended)
 
Skills Gained
After completing this workshop, you will be able to:
- Understand the basic terminologies used in partial reconfiguration terminology
 - List the fundamental steps involved in developing a design capable of partial reconfiguration
 - Learn capabilities of and restrictions imposed by the reconfiguration tools
 - Design reconfigurable systems which use embedded processor in Zynq™
 - Implement a Partial Reconfiguration system using various techniques including direct JTAG programming, accessing PCAP from the processor, accessing ICAP using AXI HWICAP IP, custom ICAP processor and the partial reconfiguration controller (PRC)
 - Use Vivado Design Suite, Vivado Analyzer and Software Development Kit (SDK) tools to design, develop, and debug a partial reconfiguration capable designs
 
Course Overview
Day 1:
- Introduction to Partial Reconfiguration (PR)
 - Introduction to Vivado for PR Designs
 - Lab 1: Introduction to Partial Reconfiguration Design Flow
- Use Vivado with Partial Reconfiguration (PR) capability enabled to synthesize HDL models and implement the design.
 
 - Use Vivado with Partial Reconfiguration (PR) capability enabled to synthesize HDL models and implement the design.
 - PR Design Considerations
 - Partial Reconfiguration Controller (PRC)
 - Debugging Using Vivado Analyzer
 - Lab 2: Using PRC for Hardware Trigger and Debug
- Use the Partial Reconfiguration Controller (PRC) core to reconfigure a design that has one RP having two RMs. Use the Vivado logic analyzer cores to debug the design.
 
 - Use the Partial Reconfiguration Controller (PRC) core to reconfigure a design that has one RP having two RMs. Use the Vivado logic analyzer cores to debug the design.
 - Embedded Design in Zynq
 
Day 2:
- Lab 3: Reconfigurable Processor Peripheral
- Use Vivado IPI and Software Development Kit to create a reconfigurable peripheral using ARM Cortex-A9 processor system in Zynq.
 
 - Use Vivado IPI and Software Development Kit to create a reconfigurable peripheral using ARM Cortex-A9 processor system in Zynq.
 - Using HWICAP IP
 - Lab 4: Reconfiguring using AXI HWICAP
- Use an AXI HWICAP IP to create a reconfigurable design.
 
 - Use an AXI HWICAP IP to create a reconfigurable design.
 - Driving ICAP using Custom ICAP Processor
 - Lab 5: Reconfiguring User Logic Using Custom ICAP Processor
- Use the provided light-weight custom IP to access the ICAP resource to reconfigure the design.
 
 - Use the provided light-weight custom IP to access the ICAP resource to reconfigure the design.
 - Advanced Features of the PRC
 - Lab 6: Reconfiguring with HW-SW Triggers Using PRC
- Use thePRC core to reconfigure a design through both hardware and software triggers.
 
 
Common to ZedBoard and ZYBO
- Lab Source Files
 - Labdocs (PDF)
 - Labdocs & Presentation (docx and pptx)*
 
ZedBoard
ZYBO
- README
 - Board Files (required to do the labs)
 
Common to ZedBoard and ZYBO
- Lab Source Files
 - Labdocs (PDF)
 - Labdocs & Presentation (docx and pptx)*
 
ZedBoard
ZYBO
- README
 - Board Files (required to do the labs)
 
ZedBoard
- README
 - Lab Source Files
 - Labdocs (PDF)
 - Labdocs & Presentation (docx and pptx)*
 
ZYBO
- README
 - Board Files (required to do the labs)
 - Lab Source Files
 - Labdocs (PDF)
 - Labdocs & Presentation (docx and pptx)*
 
Partial Reconfiguration feature is separately enabled through a license. Learn more about obtaining a license.