Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
par: AMD
The AMD LogiCORE™ 800G IEEE 802.3df Reed-Solomon Forward Error Correction (RS-FEC) IP core implements the FEC functions within the Physical Coding Sublayer (PCS) for 800GBASE-R PHYs as described in Clause 172 of IEEE Standard for Ethernet.
The AMD LogiCORE™ 800G IEEE 802.3df Reed-Solomon Forward Error Correction (RS-FEC) IP core implements the FEC functions within the Physical Coding Sublayer (PCS) for 800GBASE-R PHYs as described in Clause 172 of IEEE Standard for Ethernet (IEEE Std 802.3-2024).
Full access to this IP core, including bitstream generation capability, requires that you generate and install a Full License Key.
Please refer to the Supported Tools Version tab for this core for information on:
Software and system requirements Licensing terms and conditions for evaluation
This core is licensed under the following terms: Core License Agreement.
To purchase a LogiCORE™ IP core, contact your local Sales Representative referencing the appropriate part number(s) in the table below:
Description | License Key | Part Number |
LogiCORE™ 800G IEEE 802.3df Reed-Solomon Forward Error Correction, Site License | ieee802d3_800g_rs_fec | EF-DI-800G-RS-FEC-SITE |
LogiCORE™ 800G IEEE 802.3df Reed-Solomon Forward Error Correction, Project License | ieee802d3_800g_rs_fec | EF-DI-800G-RS-FEC-PROJ |
LogiCORE™ | Version | Software Support | Device Families |
800G IEEE 802.3df Reed-Solomon Forward Error Correction | v1.0 | Vivado™ 2025.1 | AMD Versal™ Premium |
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.