Course Description

This course introduces the AMD Versal™ adaptive SoC architecture and design methodology. This is a one-day version of the Designing with the Versal Adaptive SoC: Architecture and Designing with the Versal Adaptive SoC: Design Methodology On-Demand courses available for purchase. The lab instructions and lab files for this course are available for download here.

On-Demand Training
1 Introduction and Portfolio Overview
Describes the need for Versal devices and offers an overview of the Versal portfolio.
2 Architecture Overview
Provides a high-level overview of the Versal architecture, illustrating the various compute resources available in the Versal architecture.
3 Design Tool Flow
Maps the various compute resources in the Versal architecture to the tools required and describes how to target them for final image assembly.
4 Processing System
Reviews the Arm® Cortex® APUs and RPUs that form the processing system. The platform management controller (PMC), processing system manager (PSM), I/O peripherals, and PS-PL interfaces are also covered.
5 NoC Introduction and Concepts
Covers the reasons to use the network on chip, its basic elements, design entry flows, and common terminology.
Perform the "NoC Introduction and Concepts" lab after completing this module.
6 AI Engine
Discusses the AI Engine array architectures (AIE, AIE-ML, and AIE-ML v2), terminology, and AIE interfaces. Also lists the key differences between the AIE, AIE-ML, and AIE-ML v2 architectures.
7 SelectIO Resources
Describes the I/O bank, SelectIO™ interface, and I/O delay features.
8 System Simulation
Explains how to perform system-level simulation in a Versal device design.
Perform the "System Simulation" lab after completing this module.
9 Application Mapping and Partitioning
Covers the system design methodology and describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal adaptive SoC. Also describes what application partitioning is and how an application can be accelerated by using the various compute domains in the Versal device.