AMD Vivado™ Meeting Fmax Targets

Overview

Achieving your Fmax target in a high-speed design is one of the most challenging phases of the hardware design cycle. AMD Vivado™ brings unique features such as Report QoR Assessment (RQA), Report QoR Suggestions (RQS) and ntelligent Design Runs (IDR) –these features help you close timing. Using RQA, RQS and IDR will help converge on your performance goals in days instead of weeks resulting in huge productivity gains.

Report QoR Assessment (RQA)

The Report QoR Assessment (RQA) feature predicts a design's likelihood of meeting timing goals. It reports a simple score from 1 to 5 that indicates the degree of likelihood, 1 being least likely and 5 being most likely. In addition to an assessment score, RQA indicates the types of issues responsible for the score, the summary of methodology violations, and suggests next steps for improving a low assessment score. When run early in the compilation process, RQA helps determine whether to proceed with compilation or avoid wasted effort when chances of compilation success are minuscule.

Report QoR Suggestions (RQS)

The Vivado Design Suite also comes with another utility called Report QoR Suggestions (RQS). When the assessment is poor, RQS can be run to get suggestions on how to improve the design to get timing closure. You can use RQS to improve your score, say from a 1/2/3/4 to a better score, to improve the chances of meeting your performance goals.

The RQS report includes a summary of critical, warning, and advisory issues in the UltraFast™ methodology report (report_methodology). If you haven’t run the methodology report, then you will get a reminder to run and review the report. Addressing and fixing issues in the methodology report is the first step to ensure that the design can meet performance requirements.

The added advantage of RQS is that it not only analyses the design for issues which limit performance but also generates corrective constraints and tool options to quickly get the design to meet performance goals.

For more information on Automated Design Closure with RQA and RQS, refer to UG906 Chapter 8.

Intelligent Design Runs (IDR)

Intelligent Design Runs (IDR) is an automated timing closure flow that helps you meet timing. The capability results in significant productivity gains at the cost of increased compile time, which can be 3x-5x greater than a default Vivado compile.

Vivado uses machine learning (ML) optimized learnings to estimate delays, congestion and recommend constraints that can help a design meet its timing goals. IDR for timing closure is an aggressive timing closure implementation run where the goal is meeting the design’s performance objectives.

IDR implements tool options and directives predicted by these ML strategies. By running these ML strategies QoR fluctuations from any single run are smoothed out.

IDR is split into 3 stages:

The benchmark below shows the IDR results in 2023.1 version of the Vivado Design Suite for Versal™ Monolithic devices. The Red line shows the percentage improvement of IDR runs over the Baseline runs. The Blue bar shows the 8% average improvement over 45 customer designs.