by: AMD
The Controller Area Network (CAN) LogiCORE™ IP product provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM® CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6.
Included with CAN IP Solutions.
The Controller Area Network (CAN) LogiCORE™ IP product provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM® CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6. This PLB slave interface supports single beat read and write data transfers (no burst transfers).
Hardware Evaluation Time Out Period * : ~ 6 hrs
| LogiCORE™ | Version | Software Support | Supported Device Families |
|---|---|---|---|
| XPS CAN | v3.01a | ISE™ 12.2 EDK™ 12.2 |
Virtex™ 6 Virtex 5 SXT / LXT Virtex 5 LX Virtex 4 FX / SX / LX Spartan™ 6/ XA Spartan 3A DSP/XA Spartan 3AN Spartan 3A/XA Spartan 3E/XA Spartan 3/XA |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.