Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
par: AMD
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer core.
The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer core. This IP solution is provided in netlist form with supporting example design code. The Gen 2 IP supports 1x, 2x, and 4x lane widths. It comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design, which allows complete flexibility in selection functional blocks needed for a given application. This solution supports Verilog design environment. This IP core utilizes AXI-4 Streaming interface for data path and AXI-4 Lite interface for configuration (maintenance) transactions. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.
For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) LogiCORE IP, please visit Serial RapidIO LogiCORE IP
Hardware Evaluation Time Out Period * : ~ 8 hrs
| LogiCORE™ | Version | AXI-Support | Software Support | Supported Device Families |
|---|---|---|---|---|
| Serial RapidIO IP Gen 2 | v4.1 | AXI-4 Stream AXI-Lite |
Vivado™ 2023.2 | Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 / -2L Virtex 7 / -2L / XT |
| Serial RapidIO IP Gen 2 | v1.7 | AXI-4 Stream AXI-Lite |
ISE™ 14.5 | Artix 7 Kintex 7 / -2L Virtex 7 / -2L / XT / HT Virtex 6 HXT / LXT / SXT / CX |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.