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LogiCORE™IP Serial RapidIO Gen 2

作成者: AMD

パーツ番号:
- EF-DI-RIO-SITE
デザインツールサポート: ISE Design Suite, Vivado Software
ライセンス: Core License Agreement
デバイスサポート: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 6, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq 7000, Zynq UltraScale+ MPSoC

注文

IP の評価

Overview
Documentation
Supported Tool Versions

Product Description

The LogiCORE™ IP Serial RapidIO Gen 2 Endpoint solution, designed to RapidIO Gen 2.1 specification, comprises of a highly flexible and optimized Serial RapidIO Physical Layer core and a Logical (I/O) and Transport Layer core. This IP solution is provided in netlist form with supporting example design code. The Gen 2 IP supports 1x, 2x, and 4x lane widths. It comes with a configurable buffer design, reference clock module, reset module, and configuration fabric reference design, which allows complete flexibility in selection functional blocks needed for a given application. This solution supports Verilog design environment. This IP core utilizes AXI-4 Streaming interface for data path and AXI-4 Lite interface for configuration (maintenance) transactions. This core is designed to ensure predictable timing, thereby significantly reducing engineering time investment and allowing resources to be focused on user-specific application logic.

For Serial RapidIO Gen 1.3 (with extensions for Gen 2 5G line rates) LogiCORE IP, please visit Serial RapidIO LogiCORE IP

Key Features and Benefits

1x, 2x, & 4x Serial PHY - supports Artix™ 7, Kintex™ 7, Zynq™ 7000, Virtex™ 7, and Virtex 6 FPGAs
1x, 2x & 4x Serial PHY - supports 1.25, 2.5, 3.125, 5.0, and 6.25 Gbps line speed
Supports IDLE1 and IDLE2 sequence
Supports Packet Retry, stomp, transmission error recovery, throttle-based flow control and CRC
Support for 8/16 bit device IDs, programmable source ID on all outgoing packets
Support for priority based re-transmit suppression
Independently configurable 8/16/32 packet deep TX and RX buffer depths
AXI4-Stream interface for Data path and AXI4-Lite for the configuration Interface

Resource Utilization

Resource Utilization for Serial RapidIO Gen2

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG007 - Serial RapidIO Gen2 Endpoint v4.1 Product Guide (PG007) (v4.1)

The Serial RapidIO Gen2 Endpoint Solution (SRIO Gen2 Endpoint) comprises a highly flexible and optimized Serial RapidIO Gen2 Physical Layer and a Serial RapidIO Gen2 Logical (I/O) and Transport Layer.

View Product Guide