Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The Reed-Solomon Encoder LogiCORE™ module is a high speed, compact design that implements many different Reed-Solomon coding standards
The Reed-Solomon Encoder LogiCORE™ module is a high speed, compact design that implements many different Reed-Solomon coding standards including G.709, DVB, ATSC, IEES, ITU-T J.83 and CCSDS. The core is fully synchronous, using a single clock, and supports continuous output data with no gap between code blocks. The core is parameterizable, allowing designers to control the symbol width and the code block length. This module supports shortened codes and any primitive field polynomial for a given symbol width. The core supports a user-configured generator polynomial.
Hardware Evaluation Time Out Period * : ~ 2-3 hrs
| LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
|---|---|---|---|---|
| Reed Solomon Encoder | v9.0 | AXI4-Stream | Vivado™ 2021.1 | Versal™ Adaptive SoC Kintex™ 7 UltraScale+™ Virtex™ 7 UltraScale+ Zynq™ 7000 UltraScale+ Kintex UltraScale™ Virtex UltraScale Artix™ 7 Kinte 7 / -2L Virtex 7 / -2L / XT |
| Reed Solomon Encoder | v9.0 | AXI4-Stream | ISE™ 14.1 | Artix 7 Kintex 7 / -2L Virtex 7 / -2L / XT Virtex 6 CXT / HXT / LXT / SXT / -1L Spartan™ 6 LXT / LX |
| Reed Solomon Encoder | v7.1 | Legacy | ISE 14.1 | Artix 7 Kintex 7 / -2L Virtex 7 / -2L / XT Virtex 6 CXT / HXT / LXT / SXT / -1L Virtex 5 LXT / SXT FXT TXT Virtex 4 FX / SX / LX Spartan 6 LX / LXT Spartan 3A / 3AN / 3A-DSP Spartan 3 / 3E |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.