Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The AMD CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control units, domain controllers, automotive test equipment, instrument clusters, sensor controls, and industrial networks requiring higher data rates than conventional CAN networks.
It is required to have a valid Bosch CAN FD protocol license before selling a device containing the AMD CAN FD IP core.
The AMD CAN FD IP core is ideally suited for automotive and industrial applications such as automotive gateways, body control units, domain controllers, automotive test equipment, instrument clusters, sensor controls, and industrial networks requiring higher data rates than conventional CAN networks. The CAN FD core is compliant to the specification ISO 11898-1/2015.
Full access to this IP core, including bitstream generation capability, requires that you generate and install a Full License Key.
Please refer to the Requirements link on the product page for this core for information on:
Two categories of Licensees are defined for the CAN FD core:
It is required to have a valid Bosch CAN FD protocol license before selling a device containing the AMD CAN FD IP core.
To purchase the CAN FD LogiCORE IP core, contact your local Sales Representative referencing the part number in the table below.
LogiCORE Product Name | Part Number |
CAN FD for Automotive Applications | EF-DI-CANFD-XA-SITE |
CAN FD for Non-Automotive Applications | EF-DI-CANFD-XC-SITE |
After purchasing a license for this core, follow the instructions in the purchase confirmation email you will receive on downloading the IP core netlist from the Licensing Site, and on generating and installing a Full license key to activate Full access to the core.
For information on New Features, Known Issues, and Patches please refer to the Installation, Licensing and release Notes document available on the Licensing Solution Center.
AMD supports Full System Hardware Evaluation. The evaluation license key for this core will enable you to parameterize, generate and instantiate this IP in your design. It will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for certain period of time, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.
Please refer to the Requirements link on the product page for this core for details on System Requirements for the Vivado™ and EDK™ configurations of this core.
Please note that the terms of the CAN LogiCORE™ IP Evaluation License Agreement apply toward your evaluation of this core.
Simulation Only Evaluation
Full System Hardware Evaluation
The procedures are the same as for the Simulation Only Evaluation, except that for the IP Catalog configuration of the core, you must additionally request and install a Full System Hardware Evaluation license key. This will allow you to generate a bitstream that you can use to program an AMD FPGA and evaluate the core in hardware for a limited amount of time.
IP Evaluation license keys in EDK are pre-programmed with a 14-month evaluation period which starts from the official release date of your particular version of EDK. You can generate EDK systems containing these Full System Hardware Evaluation cores throughout the 14-month evaluation period. When programmed into an FPGA, the evaluation cores will operate for certain period of time when running at the nominal clock frequency specified for the core.
To evaluate this core in EDK, simply:
After you purchase a license for the core, you will be able to generate a "Full" electronic license key for the latest released core version. Since the Full license key does not expire, installing it will enable you to generate new EDK systems containing the core version in question indefinitely. Systems containing the core generated with a Full license will not time out when programmed into an FPGA.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
Hardware Evaluation Time Out Period * : ~ 6 hrs
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
CAN FD | v3.0 | AXI4-Lite | Vivado™ 2020.2 | Versal™ Adaptive SoC Artix™ UltraSclae+™ Kintex™ UltraScale+ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq UltraScale Artix 7 Kintex 7 Virtex 7 Zynq 7000 |
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.