Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
发布者: AMD
The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between AXI4 and AXI4-Stream IP interfaces.
The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between the AXI4 and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also offload data movement tasks from the CPU in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. The following figure illustrates the functional composition of the core.
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
AXI DMA Controller |
v7.1 | AXI4 AXI4-Stream AXI4-Lite |
Vivado™ 2025.1 | Versal™ adaptive SoC Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 Virtex 7 |
AXI DMA Controller |
v6.03a | AXI4 AXI4-Stream AXI4-Lite |
ISE™ 14.4 EDK™ 14.4 |
Zynq 7000 Artix 7 Kintex 7 Virtex 7 Virtex 6 CXT / HXT / LXT / SXT Spartan™ 6 LXT / LX |
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