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AXI DMA Controller

The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between AXI4 and AXI4-Stream IP interfaces.

Design Tools Support: Vivado Software
Bundled With: Vivado Software
License: End User License Agreement
Device Support: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Versal Premium, Versal Prime, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq 7000, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Versions

Product Description

The AXI Direct Memory Access (AXI DMA) IP core provides high-bandwidth direct memory access between the AXI4 and AXI4-Stream IP interfaces. Its optional scatter gather capabilities also offload data movement tasks from the CPU in processor-based systems. Initialization, status, and management registers are accessed through an AXI4-Lite slave interface. The following figure illustrates the functional composition of the core.

Key Features and Benefits

AXI4 compliant
Optional Scatter/Gather Direct Memory Access (DMA) support
AXI4 data width support of 32, 64, 128, 256, 512, and 1,024 bits
AXI4-Stream data width support of 8, 16, 32, 64, 128, 256, 512, and 1,024 bits
Optional Data Re-Alignment support for streaming data widths up to 512 bits
Optional AXI Control and Status Streams
Optional Keyhole support
Optional Micro DMA support
Support for up to 64-bit addressing

Resource Utilization

AXI Direct Memory Access Resource Utilization