Vitis Embedded
Vitis Embedded
Vitis™ Embedded is a standalone embedded software development package for developing host applications running on embedded Arm processors.
The Vitis Software Platform Development Environment
The AMD Vitis™ software platform is a development environment for designs targeting FPGA fabric, Arm® processors, and AI Engines, working alongside the AMD Vivado™ Design Suite to provide a higher level of abstraction.
Vitis Software includes Vitis Embedded for C/C++ application development on Arm processors; AI Engine compilers and simulators; Vitis HLS for C/C++-based FPGA IP; Vitis Model Composer for model-based design in Simulink®; and performance-optimized libraries such as DSP, Vision, Solver, Ultrasound, and BLAS for FPGA or AI Engine deployment.
Design and Simulation Flows
Adam Taylor Presents: Step-by-Step System Design with Vitis Unified Platform
Learn to create an embedded system solution using the Vitis Unified heterogeneous system flow.
Vitis Embedded Software Development Flow
(Traditionally called Embedded SDK for previous FPGA families)
Export hardware from Vivado as a platform file
Develop application code
Debug and generate boot image
Designers who are developing C/C++ code for the Arm® embedded processor subsystem in AMD adaptive SoCs will typically use this flow.
- Hardware engineers design programmable logic and export the hardware as a Xilinx Support Archive (XSA) file using AMD Vivado™ Design Suite.
- Software engineers incorporate this hardware design information in their target platform and use the Vitis Embedded software to develop their application code.
Developers can perform all system-level verification within the Vitis Embedded software and generate boot images to launch the application.
Learn more in the Vitis Tools for Embedded Software Development section in UG1400 >
Vitis System Design Flow
(Hardware and Software)
System designers who are integrating both the software and hardware portions of their design in AMD adaptive SoCs will typically use this flow.
This flow is used to develop heterogeneous embedded system designs comprising of software applications running on Arm® embedded processors and compute kernels running on programmable logic (PL) and/or Versal™ AI Engine arrays.
This flow comprises:
- A software host application written in C/C++ and typically run on the embedded Arm processor subsystem. It uses the native API implemented by the AMD Vitis Runtime Library to interact with hardware kernels within the AMD device.
- Hardware kernels that can be generated from C++ using the AMD Vitis™ HLS tool or described directly in RTL using AMD Vivado™ Design Suite.
Learn more in the Vitis Tools for Heterogeneous System Design section in UG1393 >
AMD Alveo™ Data Center accelerator cards employ the same system design flow—the software program runs on an x86 host, and the kernels run in the FPGA on a PCIe®-attached acceleration card.
Learn more in Vitis tools for Data Center Acceleration section in UG1393 >
Vitis Heterogeneous Simulation Flow
Simulate in Your Preferred Tools
• Use existing MATLAB®, Python™, C++, or HDL testbenches
• Avoid rewriting testbenches or learning new workflows
• Accelerate algorithm-to-hardware iteration
Unified AI Engine + PL Simulation (Vitis Subsystem)
• Simulate AI Engine and PL together
• Replace fragmented flows with one consistent methodology
• Detect integration issues early
Hardware-in-the-Loop (HIL) Validation
• Shorten system-level validation time
• Stream real I/O through silicon for faster debugging
• Verify end-to-end throughput before final hardware
Tools and Libraries
What’s New in 2025.2
Enhanced Design Flow with AMD Versal™ AI Engines
- AI Engine API enhancements
- New and enhanced data types
- Programming model updates and optimizations
- New and enhanced DSP library functions
- Improved AI Engine mapper and router
Easier Verification of Versal AI Engine Designs
- Updates to Vitis Functional Simulation workflow
- Hardware-in-the-Loop using MATLAB® and Python™ testbench (early access)
- Learn more about Versal AI Engines
Enhancements to Vitis Model Composer for AIE DSP Designs
- Ease-of-use updates for super sample rate (SSR) design
- Additional blocks available for both AI Engines and HDL
- Learn more about Vitis Model Composer
Updates for Vitis IDE for Embedded Development
- Vitis Embedded now enables integration of third-party AI code assistants
- Allows the use of VS Code Editor based on Eclipse Theia
- Support for Zephyr (RTOS)
- Enhanced debug capabilities with PS trace
- Learn more about Vitis IDE