Vitis Embedded
Vitis™ Embedded is a standalone embedded software development package for developing host applications running on embedded Arm processors.
Important Note: More Flexible AMD Vivado™ Licensing in 2026.1
Starting with the 2026.1 release, AMD Vivado™ Design Suite introduces new tiered licensing options, allowing customers to pay only for the device families and features they need, while Vivado Enterprise remains unchanged.
AMD Vitis™ Unified Software Platform Licensing Structure
Vitis Embedded Software
No license required for standard embedded software development.
Vitis HLS
No license required for C synthesis/simulation; compilation of generated RTL requires a valid Vivado Design Suite license.
AI Engine Development for High-Performance DSP (AIE / AIE-ML / AIE-ML v2)
AI Engine tools license (free) & Vivado Enterprise (perpetual) or Vivado Pro (subscription) license
Vitis System Design Flows
Hardware linking and implementation requires a valid Vivado Design Suite license.
AI Engine-based devices require Vivado Enterprise (perpetual) or Vivado Pro (subscription) license.
Vitis Model Composer
Requires a Vitis Model Composer license and valid Vivado Design Suite license.
These updates provide greater flexibility across embedded, AI Engine, and system-level development workflows.
The Vitis Software Platform Development Environment
The AMD Vitis™ software platform is a development environment for designs targeting FPGA fabric, Arm® processors, and AI Engines, working alongside the AMD Vivado™ Design Suite to provide a higher level of abstraction.
Vitis Software includes Vitis Embedded for C/C++ application development on Arm processors; AI Engine compilers and simulators; Vitis HLS for C/C++-based FPGA IP; Vitis Model Composer for model-based design in Simulink®; and performance-optimized libraries such as DSP, Vision, Solver, Ultrasound, and BLAS for FPGA or AI Engine deployment.
Design and Simulation Flows
Adam Taylor Presents: Step-by-Step System Design with Vitis Unified Platform
Learn to create an embedded system solution using the Vitis Unified heterogeneous system flow.
Vitis Embedded Software Development Flow
(Traditionally called Embedded SDK for previous FPGA families)
Export hardware from Vivado as a platform file
Develop application code
Debug and generate boot image
Designers who are developing C/C++ code for the Arm® embedded processor subsystem in AMD adaptive SoCs will typically use this flow.
- Hardware engineers design programmable logic and export the hardware as a Xilinx Support Archive (XSA) file using AMD Vivado™ Design Suite.
- Software engineers incorporate this hardware design information in their target platform and use the Vitis Embedded software to develop their application code.
Developers can perform all system-level verification within the Vitis Embedded software and generate boot images to launch the application.
Learn more in the Vitis Tools for Embedded Software Development section in UG1400 >
Vitis System Design Flow
(Hardware and Software)
System designers who are integrating both the software and hardware portions of their design in AMD adaptive SoCs will typically use this flow.
This flow is used to develop heterogeneous embedded system designs comprising of software applications running on Arm® embedded processors and compute kernels running on programmable logic (PL) and/or Versal™ AI Engine arrays.
This flow comprises:
- A software host application written in C/C++ and typically run on the embedded Arm processor subsystem. It uses the native API implemented by the AMD Vitis Runtime Library to interact with hardware kernels within the AMD device.
- Hardware kernels that can be generated from C++ using the AMD Vitis™ HLS tool or described directly in RTL using AMD Vivado™ Design Suite.
Learn more in the Vitis Tools for Heterogeneous System Design section in UG1393 >
AMD Alveo™ Data Center accelerator cards employ the same system design flow—the software program runs on an x86 host, and the kernels run in the FPGA on a PCIe®-attached acceleration card.
Learn more in Vitis tools for Data Center Acceleration section in UG1393 >
Vitis Heterogeneous Simulation Flow
Simulate in Your Preferred Tools
• Use existing MATLAB®, Python™, C++, or HDL testbenches
• Avoid rewriting testbenches or learning new workflows
• Accelerate algorithm-to-hardware iteration
Unified AI Engine + PL Simulation (Vitis Subsystem)
• Simulate AI Engine and PL together
• Replace fragmented flows with one consistent methodology
• Detect integration issues early
Hardware-in-the-Loop (HIL) Validation
• Shorten system-level validation time
• Stream real I/O through silicon for faster debugging
• Verify end-to-end throughput before final hardware
Tools and Libraries
What’s New in AMD Vitis™ 2026.1
Enhanced design flow with AMD Versal™ AI Engines
(applies to AIE, AIE-ML, AIE-ML V2)
- New and enhanced DSP Library functions (including Matrix operations, e.g., Cholesky & QRD)
- AI Engine API Enhancement - New & Enhanced Data Types for Versal AI Edge Series Gen 2
- Improved AIE Compiler (e.g., code coverage for enhanced debugging & Xchess Pragma for more optimized QoR)
Easier Verification of Versal AI Engine Designs
- Vitis Functional Simulation support for C++ testbenches (EA); MATLAB® and Python™ support in production
- Production version of Vitis Hardware in the Loop (MATLAB and Python)
Enhancements to Vitis Model Composer for AIE-DSP Designs
- New AIE-based DSP library blocks including GEMM/GEMV, Hadamard, Kronecker, Tensor Product, and Function Approximation
- Enhanced HDL DSP functions including SSR FFT, Vector xFFT, enhanced FIR Compiler, and DSP58/DSPFP32 support
Updates for Vitis IDE for Embedded Development
- Enhanced debug and EoU capabilities
- Production Theia AI chat capabilities