Why Heterogeneous Simulation of AMD Versal™ AI Engines and Programmable Logic?

Heterogeneous Simulation is end-to-end simulation flow that lets engineers stay in their preferred development environment while functionally validating AI Engine + PL systems before hardware implementation. This can support verification of complex AMD Versal™ adaptive SoC designs faster and with greater confidence.

Simulate in Your Native Environment—No Testbench Rewrites

Validate hardware behavior faster by simulating directly where your algorithms are developed—without rewriting testbenches or learning new workflows.

  • Reuse existing MATLAB®, Simulink®, Python™, C++ (EA), or HDL testbenches
  • Eliminate error-prone testbench development during conversion from one environment to another
  • Accelerate algorithm-to-hardware iteration by staying in familiar tools

Simplified Heterogeneous Simulation for AI Engine + PL Systems (Vitis Subsystem)

Gain early system-level confidence with a single, unified simulation approach for heterogeneous Versal device designs.

  • Simulate AI Engine and programmable logic together
  • Replace fragmented, domain-specific flows with one consistent methodology
  • Catch integration issues earlier and reduce late-stage functional mismatches

Accelerated System Validation with Hardware-in-the-Loop (HIL)

Dramatically shorten validation cycles by combining functional simulation with real hardware execution

  • Reduce system-level validation time (compared to AMD software simulation flows)
  • Stream real I/O through silicon for faster, clearer debug insight
  • Validate end-to-end throughput and behavior before final hardware is ready

Text-Based Simulation Flow

Text-based simulation flows refer to simulation using Python, C++, RTL, and MATLAB testbenches (as opposed to graphical, model-based flows such as Simulink®).

AI Engine & Programmable Logic Heterogeneous Simulation

AMD simulation flows enable co-simulation of AI Engine and programmable logic (PL) at every stage of design—so you can validate heterogeneous AMD Versal™ adaptive SoC systems early, optimize performance faster, and reduce integration risk before going to hardware.

Hardware-in-the-Loop (HIL) Validation with MATLAB® or Python™

  • Execute the complete heterogenous designs on real silicon to validate functionality and early-stage performance
  • Fast simulation while driving the design in hardware from MATLAB and Python testbenches
  • Currently supports Versal Core (VCK190) development kit
  • A hardware-in-the-loop flow complements software simulation by exposing real timing, memory hierarchy behavior, and board-level effects that are not fully captured in software or RTL simulation, while preserving the productivity advantages of high-level MATLAB or Python test environments.

 

Text-based Simulation Flow Resources

How-to Videos on AMD YouTube channel

AMD Vitis™ Functional Simulation

Discover how to use AMD Vitis™ Functional Simulation (VFS) to validate Versal adaptive SoC designs before hardware implementation. This module explains functional simulation for AI Engine graphs and PL components in both MATLAB and Python environments. 

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Model-Based Simulation Flow

Validate heterogeneous AMD Versal™ adaptive SoC designs directly in Simulink® with unified AI Engine and programmable logic co-simulation. The heterogenous simulation flow for Vitis Model Composer described below can complement the hardware validation flow outlined in UG1483 (for steps such as hardware emulation).

AMD Vitis™ Model Composer for AI Engine and PL Co-Simulation

Vitis Model Composer lets you co-simulate AI Engine and programmable logic (PL) directly in Simulink®, so you can validate AMD Versal™ adaptive SoC designs earlier, faster, and with less risk.

Validate Complete Systems Earlier

  •  Run AI Engine and PL co-simulation from a single Simulink® testbench
  • Catch integration and performance issues early to avoid costly rework
  • Close the gap between algorithm design and hardware implementation

High-Level Design with Hardware-Accurate Results

  • Model AI Engine kernels, PL (such as LogicCore IP implementing DSP functions), and Simulink components together
  • Automatically generate AI Engine graphs targeting real AMD hardware
  • Balance abstraction with cycle-accurate and transaction-level simulation

Realistic, End-to-End System Insight

  • Simulate true data movement across AI Engine, PL, and memory using AXI interfaces
  • Validate functionality, latency, and throughput before hardware is built
  • Seamlessly integrate with the Vitis toolchain

Faster Optimization, Faster Time to Hardware

  • Quickly explore AI Engine/PL partitioning and optimize performance bottlenecks
  • Stay in Simulink using familiar visualization and debug tools
  • Reduce iterations, lower risk, and move to hardware with confidence

Model-Based Simulation Flow Resources

Vitis Model Composer Overview

This video provides an overview of the AMD Vitis™ Model Composer tool and explains how to create and simulate HDL, HLS, and AI Engine designs. In addition, we will explain how to create a heterogeneous design (that is, a design with both AI Engine and programmable logic components.

Watch Video

Additional Resources

Get Started with Hackster.io Projects (featuring Adam Taylor)

Learn to create an embedded system solution using the Vitis Unified heterogeneous system flow.

Hardware-in-the-Loop with Python™
AMD Vitis Functional Simulation with Python
AMD Vitis Subsystem (AI Engine+PL) Simulation with Vivado XSIM™
AMD Vitis Functional Simulation with MATLAB

Webinars

Hardware-in-the-Loop with Python featuring Adam Taylor

Coming Soon

Training Course

GitHub Tutorial