Proven Power Reduction with AMD UltraScale™ FPGAs
Leveraging innovations in process technology, architecture, and design tools, UltraScale FPGAs enable customers to achieve the lowest power while still meeting design performance goals.
Overview
Through careful selection of silicon process and power-conscious architecture design, AMD devices deliver power efficiency across all product portfolios, including adaptive SoC platform devices, Spartan™ 6 FPGAs, 7 series FPGAs, UltraScale™ FPGAs, UltraScale+™ FPGAs, and adaptive SoCs. With each generation, AMD broadens its power-reduction capabilities, ranging from process enhancements, architectural innovations, aggressive voltage scaling, and advanced software optimization strategies. More details on portfolio-specific capabilities, silicon process advantages, and benchmark comparisons are shown below. Power estimation, thermal models, full software support, and demonstration boards are publicly available for all families. Designing power for AMD devices is easier than ever before with comprehensive documentation, built and tested power reference designs, and powerful tools to unlock the potential of your next design to get the most out of your adaptive SoC, SoC, or FPGA.
Versal Adaptive SoC
The Versal™ adaptive SoC is the next-generation, heterogeneous compute device built on TSMC’s 7nm HK-MG FinFET process, taking the next leap in low-power and high-performance technology through architectural innovation and power-optimized blocks. The Versal AI Engine architecture delivers up to 40% power savings for compute-intensive
- Hardened block RAM, UltraRAM, and DSP blocks improve device efficiency
- More efficient DSP blocks for enhanced complex and floating-point math operations
- Unused block RAMs support power gating to avoid power leakage
- UltraRAM initialization and width configurability reduce the need for external RAM/ROM
The combination of Versal adaptive SoC hardened and programmable blocks allows designers to maximize performance per watt by including previous generation power-saving techniques, as well as improved power management, new voltage and frequency scaling, and integrated system monitoring for board-level, intelligent power management.
UltraScale+ FPGAs
Built on TSMC’s 16nm FinFET+ high-performance, low-power semiconductor process, the UltraScale+ device families deliver up to 60% overall device-level power savings over 7 series FPGAs and SoCs. Architectural enhancements include:
- Hardware-based clock gating
- Hardened block RAM cascading
- DSP block efficiencies
- Power-optimized transceivers
Through architectural innovation and dual-voltage operation of the primary core fabric, UltraScale+ families more than double the performance per watt capabilities of 7 series families by realizing power reductions while improving overall performance.
UltraScale+ FPGA power savings
| 7 Series (28nm) VNOM |
UltraScale (20nm) VNOM |
UltraScale+ (16nm) VNOM |
UltraScale+ (16nm) VLOW |
|
|---|---|---|---|---|
| Operating Voltage (VCCINT) | 1V | 0.95V | 0.85V | 0.72V |
| Normalized Facric Performance | 1.0x | 1.2x | 1.6x | 1.2x |
| Normalized Total Power | 1.0x | 0.7x | 0.8x | 0.5x |
| Performance/Watt | 1.0x | 1.7x | 2x | 2.4x |
Zynq UltraScale+ MPSoCs
In addition to all the power reducing capabilities of UltraScale+ FPGA logic, Zynq™ UltraScale+ MPSoCs utilize multiple power islands and domains within the processing system for coarse-grain and fine-grain dynamic power gating to continually adjust power consumption to performance demands—lowering overall device power.
UltraScale FPGAs
Built on TSMC’s low-power 20nm semiconductor process coupled with significant static and power gating, UltraScale FPGA families deliver up to 40% overall device-level power savings compared to 7 series FPGAs. Architectural enhancements shared with UltraScale+ devices include:
- Hardware-based clock gating
- Hardened block RAM cascading
- DSP block efficiencies
- Power-optimized transceivers
UltraScale power savings
| 7 Series (28nm) VNOM |
UltraScale (20nm) VNOM |
UltraScale+ (16nm) VNOM |
UltraScale+ (16nm) VLOW |
|
|---|---|---|---|---|
| Operating Voltage (VCCINT) | 1V | 0.95V | 0.85V | 0.72V |
| Normalized Facric Performance | 1.0x | 1.2x | 1.6x | 1.2x |
| Normalized Total Power | 1.0x | 0.7x | 0.8x | 0.5x |
| Performance/Watt | 1.0x | 1.7x | 2x | 2.4x |
7 Series FPGAs & Zynq 7000 SoCs
As the only 28nm FPGAs and SoCs fabricated on a high-performance, low-power process (28HPL), 7 series devices and Zynq 7000 SoCs offer up to 50% total power reduction over previous generation families and superior performance per watt compared to competing 28nm solutions. Architectural and block-level innovations include:
- Dynamic Function eXchange (DFX) for static power savings
- Multi-mode I/O control
- Intelligent clock gating
- Power binning and voltage scaling
Optimized Power Delivery Solutions
Power management requirements are diverse and often unique to a specific use case. As a result, no single power management design can provide the optimal solution. AMD partners with industry-leading power management companies (listed below) to provide a variety of reference designs that map to common use cases, as well as overall guidance on the power supply requirements of AMD products.
Hardware Verified Power Solutions
Hardware verified power reference designs are designed to meet all AMD power specifications for a targeted device or device family. Hardware verified reference designs ensure that a power solution has been specifically built and tested to meet AMD voltage, current, and sequencing specifications. Performance data and design files are made available by the power vendor to boost your design process.
Non-Hardware Verified Solutions
Non-hardware verified solutions are designed to meet all AMD power specifications and will meet the requirements of a targeted device or device family. Though not hardware verified, they are guaranteed by datasheet specifications.
Note: All solutions are the responsibility of the specific power vendor. Please check with the appropriate power vendor for additional information and availability.
Webinars and Application Notes
AMD Power Design Manager Purpose-built for Accurate Power Estimation of AMD Adaptive SoCs & FPGAs
Low Power Designs for FPGAs and Adaptive SoCs
Monolithic Power Systems: Power-Efficient Design for AMD Spartan™ UltraScale+™ FPGAs
Texas Instruments: How to rapidly design the power supply rails of AMD FPGAs & SoCs
XAPP1375 - Simplified Power Sequencing
XAPP1394 - Temperature Dependent Dynamic Voltage Scaling Implementation
Onsemi: Zynq UltraScale+ MPSoC Automotive power solutions to ASIL-C
Monolithic Power Systems: MPS Power Modules Offer A Compact and Ultra-Low Noise Solution for AMD Zynq UltraScale+ RFSoC
Texas Instruments: Using TPS65086x PMIC to Power AMD Zynq™ UltraScale+™ MPSoCs
Texas Instruments: Power Supply Design for AMD Versal AI Edge Series
Power Delivery Tools
AMD power delivery partners provide intuitive tools to accelerate power designs, time to market, and PDN simulations to ensure a reliable and optimal performance of power delivery.
Power Delivery Partners
Thermal Design
Understating the thermal design limits of an application varies greatly between application types and end markets, a lower power design at a high ambient can experience the same thermal challenges as a high power design at a much lower ambient and so understanding what the limits of a system are is critical for both a successful product and a cost effective product, as overdesign a thermal solution incurs extra cost and complexity to a design.
To this end AMD provides DELPHI thermal models for all of current devices, these support both Siemens Flotherm and Ansys IcePak.
Thermal simulation is a critical step in board design and as indicated in the board methodology process chart, the results of the initial estimation should be used for the thermal solution validation.
Thermal Design Partners
Not all customers have access to either the thermal simulation tools or the resources to run a thermal simulation, through the AMD Alliance program you can access partners that have Thermal design capability.
Package selection
An important part of device selection is selecting the right package for a successful thermal design. AMD devices are available in many package types to cater for different customers requirements, however from a thermal standpoint the Lidless packaging offers the best thermal performance, AMD devices are offered in the following packages:
Bare Die – Package Designator (SB/VB)
- "B" indicates Bare Die, S for 0.8mm & V for 0.92mm package pitch
Lidded - (SF/VF)
- "F" For Forged Lid, S for 0.8mm & V for 0.92mm package pitch
Lidless Package (VS/LS)
- "S" indicated the Stiffener Ring, V for 0.92mm & L for 1mm pitch
- Provides optimal Thermal Performance
Lidless Overhang Package (VI)
- "I" indicates a stiffener ring with package overhead (package substrate larger than the BGA footprint)
- "V" indicates 0.92mm package pitch
- Provides optimal Thermal Performance
Power Estimation
AMD provides best-in-class tools to estimate pre-implementation power consumption, optimize for lowest power at every design stage, and provide extensive analysis for user-guided optimization. Below are a variety of power-related and AMD industry-leading hardware and software-based tools for designers to get started today.
Start Developing on the Zynq™ UltraScale+™ MPSoC ZCU102 Evaluation Kit
The ZCU102 Evaluation Kit enables designers to jumpstart designs for Automotive, Industrial, Video and Communications applications.
Resources
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