Versal AI engine technology enables high-performance digital signal processing (DSP) requirements.
Customers working on next-generation DSP applications require tremendous compute capabilities that are not efficiently implemented in traditional FPGA architectures. Compute-intensive DSP applications such as FIR, FFT, and General Matrix Multiply can use significant amounts of DSP blocks and programmable logic resources.
This requirement can significantly reduce overall compute capacity available on traditional programmable logic devices. Simply increasing DSP blocks and programmable logic available is not a scalable solution for intensive DSP workloads, which have strict power budgets.
Versal AI Engines are designed to deliver a more efficient compute solution in these cases.
Designing high-performance DSP functions targeting AMD Versal™ AI Engines can be done using either the AMD Vitis™ development tools or by using the Vitis Model Composer flow—taking advantage of the simulation and graphical capabilities of the MathWorks Simulink® tool.
In either case, mapping the DSP application into functions to implement in the FPGA or the AI Engines or a combination of FPGA logic and AI Engines is crucial. This requires an understanding of the device capabilities as well as the overall system.
Typically, compute-intensive functions are better suited to AI Engine implementation, while functions that require data moving/re-ordering are better suited to an FPGA implementation.
In the example shown below, complex filtering and Fourier transforms are typically better suited within the AI Engine array.
Once functions have been clearly identified as AI Engine appropriate, they can be implemented into the AI Engine using any of the options below.
Note: A hybrid approach using multiple options from the list below is also possible.
The Vitis platform offers two programming environments, leveraging DSP libraries, APIs, and intrinsics
Build in C/C++
The Vitis platform has open-source building blocks for common DSP algorithms, functions, and device graphs. Use them as is for rapid testing or customize them for your needs.
C/C++ Flow
To get started with AI Engines for DSP, it is highly recommended to start with Vitis DSP Library functions (C based). While hand coding can result in a more optimized implementation, using the methods below is the fastest way to get started with AI Engines for DSP while also delivering strong performance. (A hybrid approach using multiple options from the list below is also possible)
dsplib::fft::dit1ch::fft_ifft_dit_1ch
aie::vector<int8_t, sizeTileA> A0
aie::vector<int8_t, sizeTileA> A1
Acc0 = mac16(acc0, Bbuff, 0, 0x00000000, 8, 0x3120, Abuff0, 0, 0xCC884400, 2, 0x3210);
Acc0 = mac16(acc0, Bbuff, 32, 0x00000000, 8, 0x3120, Abuff0, 0, 0xCC884400, 2, 0x3210);
Different AI Engine functions are then interconnected using graph C code, which is C++ code describing a network of multiple AI Engine tiles.
Model-Based Flow with Vitis Model Composer
The composer brings development into the MathWorks MATLAB® /Simulink® environment, where you can generate kernels for Versal AI Engines, integrate programmable logic modules, and simulate systems.
Vitis Model Composer flow
Using Vitis Model Composer allows for a graphical interconnection between the different AI Engine functions. This graphical representation can be converted push button into the graph C code by Vitis Model Composer. The robust simulation capabilities of the MathWorks Simulink environment can also be leveraged to verify the design.
To learn more about Versal AI Engine development using Vitis Model Composer, please visit the Versal AI Engine Development using Vitis Model Composer page.
Use Functional Simulation in AMD Vitis Unified Software Platform to validate Versal adaptive SoC designs before hardware implementation. Learn how functional simulation in the Vitis platform helps verify logical correctness, optimize design behavior, and streamline the path from simulation to hardware deployment.
Leverage the AMD GitHub for optimized design examples, tutorials and library functions for AI Engines in High-Performance DSP Applications.
These are open-source designs that can be leveraged to expedite design cycles.
The most popular GitHub resources for getting started with AI Engine development are:
Learn to navigate and download a design from the AMD GitHub and run it within the AMD Vitis Unified Software Platform. The flow is highlighted using a Polyphase Channelizer as an example.
The polyphase channelizer down-converts simultaneously a set of frequency-division multiplexed (FDM) channels carried in a single data stream using an efficient approach based on digital signal processing. Channelizer use is ubiquitous in many wireless communication, radar, aerospace/defense, & medical imaging systems. In this tutorial, we implement two different channelizer designs using a combination of AI Engine and programmable logic (PL) resources in AMD Versal™ Adaptive SoC devices.
While the AI Engine compiler and simulator tools are part of the AMD Vitis™ software installer, these tools still require a free license for use. You can get this license from the Product Licensing Site.
Enter your details and choose the “AI Engine Tools License” option.
Request access to benchmarks comparing Versal AI Engines to previous programmable logic technology. For head-to-head benchmark comparisons of Programmable Logic-only designs vs. an adaptive SoC + AI Engine design using AMD Versal Adaptive SoCs, please contact sales or your FAE for benchmark results and source designs.
