Accelerate DSP Workloads with Versal AI Engines
The Key to Improving Total System Performance
Unleash DSP Compute with AMD Versal™ AI Engines
Versal AI Engine technology enables high-performance digital signal processing (DSP)
Customers working on next-generation DSP applications require tremendous compute capabilities that are not efficiently implemented in traditional FPGA architectures. Compute-intensive DSP applications such as FIR, FFT, and General Matrix Multiply can use significant amounts of DSP blocks and programmable logic resources.
This algorithm complexity can significantly reduce the overall compute capacity available on traditional programmable logic devices. Simply increasing DSP blocks and programmable logic available is not a scalable solution for intensive DSP workloads, which have strict power budgets. Versal AI Engines are designed to deliver a more efficient compute solution in these cases.
Our how-to video library offers essential technical information to get started.
AI Engine DSP Design Process
Designing high-performance DSP functions targeting AMD Versal™ AI Engines can be done using either the AMD Vitis™ development tools or by using the Vitis Model Composer flow—taking advantage of the simulation and graphical capabilities of the MathWorks Simulink® tool.
In either case, mapping the DSP application into functions to implement in the FPGA or the AI Engines or a combination of FPGA logic and AI Engines is crucial. This requires an understanding of the device capabilities as well as the overall system.
Typically, compute-intensive functions are better suited to AI Engine implementation, while functions that require data moving/re-ordering are better suited to an FPGA implementation.
In the example shown below, complex filtering and Fourier transforms are typically better suited within the AI Engine array.
Once functions have been clearly identified as AI Engine appropriate, they can be implemented into the AI Engine using any of the options below.
Note: A hybrid approach using multiple options from the list below is also possible.
Programming Environments
The Vitis platform offers two programming environments, leveraging DSP libraries, APIs, and intrinsics
- Build in C/C++
- Model-Based Flow with Vitis Model Composer
Build in C/C++
The Vitis platform has open-source building blocks for common DSP algorithms, functions, and device graphs. Use them as is for rapid testing or customize them for your needs.
C/C++ Flow
To get started with AI Engines for DSP, it is highly recommended to start with Vitis DSP Library functions (C based). While hand coding can result in a more optimized implementation, using the methods below is the fastest way to get started with AI Engines for DSP while also delivering strong performance. (A hybrid approach using multiple options from the list below is also possible)
Option 1
Vitis DSP Library Function Call
dsplib::fft::dit1ch::fft_ifft_dit_1ch
- Easiest to use
- Parameterizable
- Fastest development
Option 2
Vectorized Programming with AI Engine APIs
aie::vector<int8_t, sizeTileA> A0
aie::vector<int8_t, sizeTileA> A1
- Customizable
- Faster development
Option 3
Vectorized Programming with Intrinsics
Acc0 = mac16(acc0, Bbuff, 0, 0x00000000, 8, 0x3120, Abuff0, 0, 0xCC884400, 2, 0x3210);
Acc0 = mac16(acc0, Bbuff, 32, 0x00000000, 8, 0x3120, Abuff0, 0, 0xCC884400, 2, 0x3210);
- Full, low-level customization
- Lengthiest Development
Different AI Engine functions are then interconnected using graph C code, which is C++ code describing a network of multiple AI Engine tiles.
Simulation and Verification Steps
| Design | Simulation Options |
| AI Engine only | X86 Simulator (Fast) & AIE Simulator (Cycle Approximate) |
| AI Engine + PL Subsystem (PL coded using Vitis HLS) |
Vitis Functional Simulation with MATLAB or Python |
| AI Engine + PL Subsystem (PL coded using HDL) |
Functional Simulation with HDL Testbench using Vivado™ XSIM |
| AI Engine + PL + PS | Hardware Emulation in Vitis PS Simulated using QEMU PL Simulating using XSIM (HDL Test Bench) AIE Simulated using AIE Simulator (System C) |
For more information on Simulation Flows, please refer to: Versal Adaptive SoC Design Guide (UG1273)
Model-Based Flow with Vitis Model Composer
The composer brings development into the MathWorks MATLAB® /Simulink® environment, where you can generate kernels for Versal AI Engines, integrate programmable logic modules, and simulate systems.
Vitis Model Composer flow
Using Vitis Model Composer allows for a graphical interconnection between the different AI Engine functions. This graphical representation can be converted push button into the graph C code by Vitis Model Composer. The robust simulation capabilities of the MathWorks Simulink environment can also be leveraged to verify the design.
To learn more about Versal AI Engine development using Vitis Model Composer, please visit the Versal AI Engine Development using Vitis Model Composer page.
Vitis GitHub Design Examples and Tutorials
AMD Vitis Design Implementation
Leverage the AMD GitHub for optimized design examples, tutorials and library functions for AI Engines in High-Performance DSP Applications. These are open-source designs that can be leveraged to expedite design cycles.
GitHub Links
Resources
How-To Videos
Webinars
Documentation
Training Courses
Get Started
Licensing the AI Engine Tools: Compiler and Simulator
While the AI Engine compiler and simulator tools are part of the AMD Vitis™ software installer, these tools still require a free license for use. You can get this license from the Product Licensing Site.
Enter your details and choose the “AI Engine Tools License” option.
Access Benchmarks Comparing Versal AI Engines to Previous Programmable Logic Technology
For head-to-head benchmark comparisons of Programmable Logic-only designs vs. an adaptive SoC + AI Engine design using AMD Versal Adaptive SoCs, please contact sales or your FAE for benchmark results and source designs.
Footnotes
- Based on 3rd party benchmark testing commissioned by AMD in February 2024, on the AMD Versal adaptive SoC with Vitis for AI design tools versus traditional programmable logic with Vivado software and Vitis Model Composer Tool, version 2023.1 in a signal processing application FIR implementation. Results averaged over 3 designs. Results will vary depending on design specifications. (VER-034)
Footnotes
- Based on 3rd party benchmark testing commissioned by AMD in February 2024, on the AMD Versal adaptive SoC with Vitis for AI design tools versus traditional programmable logic with Vivado software and Vitis Model Composer Tool, version 2023.1 in a signal processing application FIR implementation. Results averaged over 3 designs. Results will vary depending on design specifications. (VER-034)