• Zoom sur l'image
    AMD Intellectual Property

LD-based Parallel Latch

par: AMD

The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.

  • Outils de conception pris en charge: ISE Design Suite
  • Fourni avec: ISE Design Suite
  • Prise en charge des appareils: Spartan 3, Spartan 3E, Virtex FPGAs, Virtex E, Virtex II, Virtex II Pro