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    AMD Intellectual Property

LD-based Parallel Latch

作者: AMD

The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.

  • 設計工具支援: ISE Design Suite
  • 隨附於: ISE Design Suite
  • 器件支援: Spartan 3, Spartan 3E, Virtex FPGAs, Virtex E, Virtex II, Virtex II Pro