ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
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影像縮放
LD-based Parallel Latch
作者: AMD
The LD-based Parallel Latch IP core is a latch-based data register with 1 to 64 bits width.
- 设计工具支持: ISE Design Suite
- 捆绑产品: ISE Design Suite
- 器件支持: Spartan 3, Spartan 3E, Virtex FPGAs, Virtex E, Virtex II, Virtex II Pro