What is Vitis Model Composer?

AMD Vitis™ Model Composer is a high-level design and simulation tool that bridges algorithm development and hardware implementation. It integrates deeply with MathWorks MATLAB® and Simulink®, allowing developers to:

  • Design and simulate hardware-accelerated algorithms graphically within Simulink.
  • Perform early design space exploration without needing to write low-level HDL or AI Engine C code initially.
  • Generate synthesizable hardware IP directly from MATLAB/Simulink models targeted for AMD adaptive SoCs and FPGAs, including the latest Versal™ devices with AI Engines.

Vitis Model Composer is available as an add-on license that works alongside the AMD Vivado™ Design Suite (Standard or Enterprise) and the AMD Vitis™ Unified Software Platform. It is especially helpful for algorithm developers who prefer a model-based design approach and want to accelerate the transition from algorithm to hardware implementation.

Core Features of Vitis Model Composer

Use the MATLAB and Simulink environment to analyze and visualize your design:

  • Use optimized AI Engine, HLS, and HDL blocks directly from the Simulink library browser
  • Import custom AI Engines, HLS, and HDL code as blocks
  • Run fast simulations in the Simulink environment
  • Compare the results with golden references in the MATLAB and Simulink environment
  • Tap into intermediate signals to debug and get visibility into the design

Co-simulate a heterogeneous system:

  • Directly use optimized AI Engines/HLS/Programmable Logic (PL) from the library browser or import code as blocks
  • Seamlessly connect AI Engine arrays with HLS kernel blocks or HDL blocks

Increase productivity by generating code from your design:

  • Generate graph code along with constraints
  • Generate RTL (Verilog/VHDL)
  • Generate optimized HLS code with inserted pragmas
  • Generate a testbench

Easily validate your design in hardware:

  • Generate data movers, processing system code, config files
  • Generate the makefiles to build the design for hardware
  • Move the design into hardware with the click of a button

Creating and Simulating Vitis Model Composer Designs

Get an overview of the AMD Vitis™ Model Composer tool and learn how to create and simulate HDL, HLS, and AI Engine designs. In addition, we will explain how to create a heterogeneous design (that is, a design with both AI Engine and programmable logic components).

Using the AMD Vitis™ Model Composer Hub Block

An introduction to the AMD Vitis Model Composer Hub block. You will learn how to use the block to select hardware, generate code, analyze and verify a design, and finally validate on hardware.

Designing with Versal AI Engines in Vitis Model Composer

Versal AI Engines are specialized compute units optimized for machine learning, DSP, and signal processing tasks on AMD adaptive SoCs. Vitis Model Composer enables effective use of these AI Engines by providing:

AI Engine Library Blocks

  • Prebuilt AI Engine IP Blocks: Includes ready-to-use DSP and signal processing blocks such as:
    • FIR filters (Finite Impulse Response)
    • FFT (Fast Fourier Transform) and iFFT
    • DDS (Direct Digital Synthesis)
    • Mixers

These blocks model the functionality of AI Engines and allow designers to quickly prototype and simulate AI Engine-based algorithms.

Kernel Import and Dataflow Integration

  • Custom Kernel Import: Users can import custom AI Engine kernels (written in C++ or HLS) as blocks into Simulink. This enables mixing custom AI Engine code with graphical models.
  • Dataflow Graph Import: Supports importing AI Engine dataflow graphs, allowing users to configure and connect complex AI Engine compute pipelines visually.

Mixed-Design Simulation

  • Vitis Model Composer supports mixed simulation where AI Engine blocks operate alongside programmable logic blocks (HDL or HLS). This lets designers verify system-level interactions, timing, and data movement across heterogeneous compute resources.

Visualization and Debug

  • Simulink source and sink blocks can connect directly with AI Engine blocks to monitor and visualize signals during simulation.
  • Support for cycle-approximate simulation helps in early performance estimation of AI Engine workloads.

What's New

2025.2 Release Highlights

Additional blocks available for both AI Engine and HDL

AIE, AIE-ML, AIE-ML v2 (e.g., Versal AI Core and AI Edge Series, and Versal AI Edge Series Gen2)

  • New: Function Approximation​
  • New: Correlation/Convolution​
  • New: Cumulative Sum

HDL Library Blocks​

  • Enhanced: FFT (Added native floating-point SSR = 32, 64)​
  • Enhanced: FIR (Support fractional rate interpolation with SSR)

Other Vitis Model Composer Enhancements

  • HLS-AIE bridge blocks support modeling of multirate systems – provides efficient method to model designs with different clock domains and safely transfer data without corruption​
  • Added support for MATLAB® R2025b​
  • Added support for Red Hat® Enterprise Linux® (RHEL) 9.6, 10.0

Support for multiple top-level AI Engine subsystems

Additional Blocks available for both AI Engine and HDL

AI Engine

  • Bitonic sort (Versal AI Core Series, Versal AI Edge Series, Versal AI Edge Series Gen2)
  • DFT/ FFT (Versal AI Edge Series Gen2)
  • FIR – Single rate, half-band, rate change, fractional resampler (Versal AI Edge Series Gen2)
  • DDS/mixer (Versal AI Edge Series Gen2)

HDL Library

  • Enhanced FFT – Additional SSR modes
    • SSR 8, 16, 32, 64 (native floating point)
    • SSR 2, 4 (fixed point)
  • Enhanced complex multiplier – Fewer DSP58 resources
    • New support for CFLOAT MAC
    • Vector IFFT float – new block

Versal AI Engine DSP Library Updates for Vitis Model Composer​​:

  • AIE​ (Available on Versal AI Core, Versal Premium Series) 
    • Mixed Radix FFT​ 
    • Stockham FFT Performance Enhancements​ 
    • TDM FIR​ 
  • AIE-ML​ (Available on Versal AI Edge Series) 
    • TDM FIR​ 
    • DDS (Direct Digital Synthesis – used for waveform generation)​ 
    • Mixer (used for frequency shifting)​ 
  • AIE-MLv2​ (Available on Versal AI Edge Gen 2 Series) 
    • FIR​ 
    • DFT​ 
    • DDS​ 
    • Mixer 

GitHub - Xilinx/Vitis_Model_Composer at 2024.2

New HDL Blocks in Vitis Model Composer​:

  • Simple dual-port RAM (new block) 
  • Direct Digital Synthesis (DDS) compiler (Added native floating-point support) 
  • FFT 
    • Added native floating-point support with SSR=2, 4 
    • Maps to DSPFP32 primitive on Versal devices 

Other Enhancements

  • Use Vitis Debugger with AIE/HLS Kernels built in Vitis Model Composer 
  • Export Vitis Subsystem from Vitis Model Composer as a .vss file 
  • Additional data types for Vitis Model Composer 
    • Support for cbfloat16 
    • Support for cascaded signals: int8/uint8, int16/uint16/cint16, int32, uint32, cint32, float/cfloat 
  • Design rule checks (DRCs) to assist in detection and indication of design issues early in the build process (e.g., simulation) 
  • Fast response time for code generation​ 
    • Simulation runs only once for any design 
  • Save Hub block configurations as a JSON file (for batch processing, rapid prototyping, etc.)​ 

OS and MATLAB version support added with version 2024.2

  • MATLAB R2024a 
  • Red Hat Enterprise Linux® (RHEL) 8.10, 9.4 

New example designs ​available on GitHub

Download

Buy

Vitis Model Composer can be purchased as an add-on license to Vivado standard or enterprise editions and Vitis unified software platform. 
To evaluate, generate a free 90-day evaluation license from the Product Licensing Site. 

Resources

AI Engine Library

  • Lab 1: Introduction to Versal™ Adaptive and AI Engine
  • Lab 2: Build and Simulate an AI Engine Design
  • Lab 3: Import Custom AI Engine code
  • Lab 4 : AI Engine Code Generation and Cycle- Approximate Simulation
  • Lab 5 : AI Engine Designs in Vitis Analyzer
  • Lab 6 : Hardware Validation of Versal Adaptive design

HLS Library

These tutorials help you examine the Vitis Model Composer HLS library, build a simple design using HLS blocks, and learn about the data types supported by Vitis Model Composer.

HDL Library

These tutorials show you how to use the Vitis Model Composer HDL library to specify a design in Simulink® and synthesize the design into an FPGA. 

尾註
  1. Based on testing on August 10, 2023, across 1000 Vitis L2/L3 code library designs, with Vitis HLS release 2023.2 vs. Vitis HLS 2023.1. System configuration during testing: Intel Xeon E5-2690 v4 @ 2.6GHz CPU, 256GB RAM, RedHat Enterprise Linux 8.6. Actual performance will vary. System manufacturers may vary configuration, yielding different results. -VGL-04
  2. The benchmark tests were performed on all 1208 Vitis L1 library C-code designs as of February 12th, 2023. All designs were run using a system with 2P Intel Xeon E5-2690 CPUs with CentOS Linux, SMT enabled, Turbo Boost disabled. Hardware configuration not expected to effect software test results. Results may vary based on software and firmware settings and configurations- VGL-03