There are two broad classification of Debug Bridge IP functionality, which are supported using four different modes.
- Tandem with Field Updates and Partial Reconfiguration Solution – User selectable mode From_BSCAN_to_Debug is used to add a Debug Bridge instance in each Reconfigurable Module which would connect to debug cores like ILA, VIO, Memory IP, and JTAG2AXI
Virtual Cable (XVC) Solution – Three modes are supported:
- User selectable mode From_AXI_to_BSCAN is used to add a Debug Bridge instance in the design with an Ethernet/PCIe® master. This mode is a slave to Ethernet/PCIe master while connecting to debug cores like ILA, VIO, Memory IP, and JTAG2AXI in the same chip
- User selectable mode From_AXI_to_JTAG is used to add a Debug Bridge instance in the design with an Ethernet/PCIe master. This mode is a slave to Ethernet/PCIe master while bringing out the JTAG pins out of the FPGA through I/O pins. This mode is mainly used to debug design on another board over XVC.
- User selectable mode From_JTAG_to_BSCAN is used to add a Debug Bridge instance to debug the designs over soft Test Access Port (TAP) controller.
