Vivado IP Release Notes
This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.
by: AMD
The Video Timing Controller LogiCORE™ IP is a general purpose video timing detector and generator, which automatically detects blanking and active data timing based on the input horizontal and vertical synchronization pulses.
The Video Timing Controller LogiCORE™ IP is a general purpose video timing detector and generator. The core is commonly used with the Video in to AXI4-Stream IP Core to detect the format and timing of incoming video or with the AXI4-Stream to Video Out IP Core to generate outgoing video timing for downstream sinks.
The AMD Video Timing Controller LogiCORE IP is a general purpose video timing detector and generator, which automatically detects blanking and active data timing based on the input horizontal and vertical synchronization pulses. The Video Timing Controller can generate video timing signals and allows for adjustment of timing within a video design. The core is programmable through registers, provides a comprehensive set of interrupt controls, and supports multiple system configurations.
Hardware Evaluation Time Out Period * : ~ 1-8 hrs
LogiCORE™ | Version | AXI4 Support | Software Support | Supported Device Families |
---|---|---|---|---|
Video Timing Controller | v6.2 | AXI4-Lite | Vivado™ 2022.2 | Versal™ Adaptive SoC Kintex™ UltraScale+™ Virtex™ UltraScale+ Zynq™ UltraScale+ Kintex UltraScale™ Virtex UltraScale Zynq 7000 Artix™ 7 Kintex 7 Virtex 7 |
Video Timing Controller |
v5.01a | ISE™ 14.3 | Zynq 7000 Artix 7 Kintex 7 Virtex 7 / XT Virtex 6 CXT / HXT / LXT / SXT Spartan™ 6 LXT / LX |
|
Video Timing Controller | v2.1 | ISE 12.3 | Virtex 5 TXT / FXT / SXT / LXT / LX Spartan 3A DSP |
Download the required software from the AMD Downloads page. For information on New Features, Known Issues, and Patches please refer to the Licensing Solution Center.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.
Certain AMD technologies may require third-party enablement or activation. Supported features may vary by operating system. Please confirm with system manufacturer for specific features. No technology or product can be completely secure.