跳到主要內容

影像縮放

AXI Memory Initialization

作者: AMD

The AXI Memory Initialization core autonomously writes an initial value to all specified address locations after power-up and following each soft reset.

設計工具支援: Vivado Software
隨附於: Vivado Software
授權: End User License Agreement
器件支援: Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Version

Product Description

The AXI Memory Initialization core autonomously writes an initial value to all specified address locations after power-up and following each soft reset. This prevents spurious ECC errors that can occur when accessing an uninitialized memory. This could also provide security following a partial reconfiguration to prevent a process running in a new reconfigurable module from accessing data left over from an earlier run.

Key Features and Benefits

User-selectable starting address and address range size
User-selectable initial value string to aid debugging
Supports AXI4 and AXI3 protocols

Documentation

Vivado IP Release Notes

This article contains a list of all 'Vivado™ IP Release Notes - All IP Change Log Information' answer records and the associated Vivado Tools release.

View Release Note

PG341 - AXI Memory Initialization LogiCORE IP Product Guide (PG341) (v1.0)

The AXI Memory Initialization core autonomously writes an initial value to all specified address locations after power-up and following each soft reset.

View Product Guide