ISE Release Notes
This document contains a listing of release note tables, one for each IP core.
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影像縮放
Digital Clock Manager (DCM) Module
作者: AMD
The Digital Clock Manager (DCM) primitive in AMD FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum.
- 设计工具支持: ISE Design Suite
- 捆绑产品: Embedded Development Kit
- 授權: End User License Agreement
- 器件支持: Spartan 3, Virtex II, Virtex II Pro, Virtex 4