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DMA for PCI Express® (PCIe®) Subsystem

作者: AMD

DMA for PCIe® implements a high performance, configurable DMA for use with the PCI Express® Integrated Block.

设计工具支持: Vivado Software
捆绑产品: Vivado Software
授權: End User License Agreement
器件支持: Artix 7, Virtex 7, Virtex UltraScale+, Kintex 7, Kintex UltraScale+, Zynq UltraScale+ MPSoC, Zynq UltraScale+ RFSoC, Kintex UltraScale, Virtex UltraScale

Overview
Documentation
Supported Tool Version

Product Description

The AMD LogiCORE™ DMA for PCI Express® (PCIe®) implements a high performance, configurable Scatter Gather DMA for use with the PCI Express Integrated Block. The IP provides an optional AXI4-MM or AXI4-Stream user interface.

Drivers

Reference drivers are available at QDMA IP Drivers and XDMA Windows Driver Secure Site Request.

Key Features and Benefits

DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices. Support for 64 and 128-bit datapath for Virtex™ 7 XT devices
Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex 7 XT devices
Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex 7 XT devices
64-bit source, destination, and descriptor addresses
Per channel descriptor bypass for custom descriptor creation
Configurable user interface
- Common AXI4 memory mapped (MM) user interface
- A separate AXI4-Stream user interface
AXI Master interfaces enable PCIe reads and writes to bypass the DMA engine

Resource Utilization

DMA/Bridge Subsystem for PCI Express Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

PG195 - DMA/Bridge Subsystem for PCI Express Product Guide (PG195) (v4.1)

The AMD DMA Subsystem for PCI Express® implements a high performance, configurable Scatter Gather DMA for use with the PCI Express 3.x/4.x Integrated Block. The IP provides an optional AXI4 or AXI4-Stream user interface.

View Product Guide