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AXI SmartConnect

作者: AMD

The AMD LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

設計工具支援: Vivado Software
隨附於: Vivado Software
授權: End User License Agreement
器件支援: Artix 7, Kintex 7, Kintex UltraScale, Kintex UltraScale+, Virtex 7, Virtex UltraScale, Virtex UltraScale+, Zynq UltraScale+ MPSoC

Overview
Documentation
Supported Tool Version

Product Description

The AMD LogiCORE™ IP AXI SmartConnect core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

The AXI SmartConnect is a Hierarchical IP block that is added to a Vivado™ IP Integrator block design in the Vivado Design Suite.

AXI SmartConnect is a drop-in replacement for the AXI Interconnect v2 core. AXI SmartConnect is more tightly integrated into the Vivado design environment to automatically configure and adapt to connected AXI master and slave IP with minimal user intervention.

Key Features and Benefits

Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI) per instance
Instances of SmartConnect can be cascaded to interconnect a larger number of masters/slaves or for organizing the interconnect topology
AXI Protocol compliant
Burst transactions are automatically split, as needed, to remain AXI compliant
Interface Data Widths (bits):
- AXI4 and AXI3: 32,64,128,256,512 or 1024
- AXI4-Lite: 32 or 64-bit
Transactions between interfaces of different data widths are automatically converted by AXI SmartConnect

Resource Utilization

AXI SmartConnect Resource Utilization

Documentation

Vivado Release Notes

The most updated Release Note.

View Release Note

PG247 - SmartConnect (PG247) (v1.0)

Connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

View Product Guide smartconnect.html